29 #ifndef __STM32F4x7_ETH_BSP_H
30 #define __STM32F4x7_ETH_BSP_H
38 #if defined (USE_STM324xG_EVAL)
39 #include "stm324xg_eval.h"
40 #include "stm324xg_eval_lcd.h"
42 #elif defined (USE_STM324x7I_EVAL)
43 #include "stm324x7i_eval.h"
44 #include "stm324x7i_eval_lcd.h"
48 #if USE_LWIP || USE_ETHERNET
49 #include "config/eth_conf.h"
56 #define ETH_LINK_EXTI_LINE EXTI_Line14
57 #define ETH_LINK_EXTI_PORT_SOURCE EXTI_PortSourceGPIOB
58 #define ETH_LINK_EXTI_PIN_SOURCE EXTI_PinSource14
59 #define ETH_LINK_EXTI_IRQn EXTI15_10_IRQn
61 #define ETH_LINK_PIN GPIO_Pin_14
62 #define ETH_LINK_GPIO_PORT GPIOB
63 #define ETH_LINK_GPIO_CLK RCC_AHB1Periph_GPIOB
66 #define ETH_INIT_FLAG 0x01
67 #define ETH_LINK_FLAG 0x10
72 uint32_t Eth_Link_PHYITConfig(uint16_t PHYAddress);
73 void Eth_Link_EXTIConfig(
void);
74 void Eth_Link_IT_task(
void * pvParameters);
75 void Eth_Link_EXTIConfig(
void);
79 #include "lwip/lwip/netif.h"
80 void ETH_link_callback(
struct netif *netif);
84 #define _eth_delay_ ETH_Delay
87 #define LAN8720_PHY_ADDRESS 0x00
125 #define PHY_RESET_DELAY ((uint32_t)0x000000FF)
127 #define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
129 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
132 #define PHY_RESET_DELAY ((uint32_t)0x000FFFFF)
134 #define PHY_CONFIG_DELAY ((uint32_t)0x00FFFFFF)
136 #define ETH_REG_WRITE_DELAY ((uint32_t)0x0000FFFF)
145 #define PHY_SR ((uint16_t)0x10)
146 #define PHY_SPEED_STATUS ((uint16_t)0x0002)
147 #define PHY_DUPLEX_STATUS ((uint16_t)0x0004)
150 #define PHY_MICR ((uint16_t)0x11)
151 #define PHY_MICR_INT_EN ((uint16_t)0x0002)
152 #define PHY_MICR_INT_OE ((uint16_t)0x0001)
155 #define PHY_MISR ((uint16_t)0x12)
156 #define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020)
157 #define PHY_LINK_STATUS ((uint16_t)0x2000)
BSP - Board Support Package.
libheivs configuration file
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...