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stm32f4xx_rcc.h
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1 /**
2  ******************************************************************************
3  * @file stm32f4xx_rcc.h
4  * @author MCD Application Team
5  * @version V1.0.0
6  * @date 30-September-2011
7  * @brief This file contains all the functions prototypes for the RCC firmware library.
8  ******************************************************************************
9  * @attention
10  *
11  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17  *
18  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
19  ******************************************************************************
20  */
21 
22 /* Define to prevent recursive inclusion -------------------------------------*/
23 #ifndef __STM32F4xx_RCC_H
24 #define __STM32F4xx_RCC_H
25 
26 #ifdef __cplusplus
27  extern "C" {
28 #endif
29 
30 /* Includes ------------------------------------------------------------------*/
31 #include "stm32/stm32f4xx.h"
32 
33 /** @addtogroup STM32F4xx_StdPeriph_Driver
34  * @{
35  */
36 
37 /** @addtogroup RCC
38  * @{
39  */
40 
41 /* Exported types ------------------------------------------------------------*/
42 typedef struct
43 {
44  uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
45  uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
46  uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
47  uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
48 }RCC_ClocksTypeDef;
49 
50 /* Exported constants --------------------------------------------------------*/
51 
52 /** @defgroup RCC_Exported_Constants
53  * @{
54  */
55 
56 /** @defgroup RCC_HSE_configuration
57  * @{
58  */
59 #define RCC_HSE_OFF ((uint8_t)0x00)
60 #define RCC_HSE_ON ((uint8_t)0x01)
61 #define RCC_HSE_Bypass ((uint8_t)0x05)
62 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
63  ((HSE) == RCC_HSE_Bypass))
64 /**
65  * @}
66  */
67 
68 /** @defgroup RCC_PLL_Clock_Source
69  * @{
70  */
71 #define RCC_PLLSource_HSI ((uint32_t)0x00000000)
72 #define RCC_PLLSource_HSE ((uint32_t)0x00400000)
73 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
74  ((SOURCE) == RCC_PLLSource_HSE))
75 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
76 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
77 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
78 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
79 
80 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
81 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
82 /**
83  * @}
84  */
85 
86 /** @defgroup RCC_System_Clock_Source
87  * @{
88  */
89 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
90 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
91 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
92 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
93  ((SOURCE) == RCC_SYSCLKSource_HSE) || \
94  ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
95 /**
96  * @}
97  */
98 
99 /** @defgroup RCC_AHB_Clock_Source
100  * @{
101  */
102 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
103 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
104 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
105 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
106 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
107 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
108 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
109 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
110 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
111 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
112  ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
113  ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
114  ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
115  ((HCLK) == RCC_SYSCLK_Div512))
116 /**
117  * @}
118  */
119 
120 /** @defgroup RCC_APB1_APB2_Clock_Source
121  * @{
122  */
123 #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
124 #define RCC_HCLK_Div2 ((uint32_t)0x00001000)
125 #define RCC_HCLK_Div4 ((uint32_t)0x00001400)
126 #define RCC_HCLK_Div8 ((uint32_t)0x00001800)
127 #define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
128 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
129  ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
130  ((PCLK) == RCC_HCLK_Div16))
131 /**
132  * @}
133  */
134 
135 /** @defgroup RCC_Interrupt_Source
136  * @{
137  */
138 #define RCC_IT_LSIRDY ((uint8_t)0x01)
139 #define RCC_IT_LSERDY ((uint8_t)0x02)
140 #define RCC_IT_HSIRDY ((uint8_t)0x04)
141 #define RCC_IT_HSERDY ((uint8_t)0x08)
142 #define RCC_IT_PLLRDY ((uint8_t)0x10)
143 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
144 #define RCC_IT_CSS ((uint8_t)0x80)
145 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
146 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
147  ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
148  ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
149  ((IT) == RCC_IT_PLLI2SRDY))
150 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
151 /**
152  * @}
153  */
154 
155 /** @defgroup RCC_LSE_Configuration
156  * @{
157  */
158 #define RCC_LSE_OFF ((uint8_t)0x00)
159 #define RCC_LSE_ON ((uint8_t)0x01)
160 #define RCC_LSE_Bypass ((uint8_t)0x04)
161 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
162  ((LSE) == RCC_LSE_Bypass))
163 /**
164  * @}
165  */
166 
167 /** @defgroup RCC_RTC_Clock_Source
168  * @{
169  */
170 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
171 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
172 #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
173 #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
174 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
175 #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
176 #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
177 #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
178 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
179 #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
180 #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
181 #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
182 #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
183 #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
184 #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
185 #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
186 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
187 #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
188 #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
189 #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
190 #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
191 #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
192 #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
193 #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
194 #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
195 #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
196 #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
197 #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
198 #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
199 #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
200 #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
201 #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
202 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
203  ((SOURCE) == RCC_RTCCLKSource_LSI) || \
204  ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
205  ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
206  ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
207  ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
208  ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
209  ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
210  ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
211  ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
212  ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
213  ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
214  ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
215  ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
216  ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
217  ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
218  ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
219  ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
220  ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
221  ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
222  ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
223  ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
224  ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
225  ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
226  ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
227  ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
228  ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
229  ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
230  ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
231  ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
232  ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
233  ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
234 /**
235  * @}
236  */
237 
238 /** @defgroup RCC_I2S_Clock_Source
239  * @{
240  */
241 #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
242 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
243 
244 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
245 /**
246  * @}
247  */
248 
249 /** @defgroup RCC_AHB1_Peripherals
250  * @{
251  */
252 #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
253 #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
254 #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
255 #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
256 #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
257 #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
258 #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
259 #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
260 #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
261 #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
262 #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
263 #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
264 #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
265 #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
266 #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
267 #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
268 #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
269 #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
270 #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
271 #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
272 #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
273 #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
274 #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
275 #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
276 #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
277 #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))
278 /**
279  * @}
280  */
281 
282 /** @defgroup RCC_AHB2_Peripherals
283  * @{
284  */
285 #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
286 #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
287 #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
288 #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
289 #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
290 #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
291 /**
292  * @}
293  */
294 
295 /** @defgroup RCC_AHB3_Peripherals
296  * @{
297  */
298 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
299 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
300 /**
301  * @}
302  */
303 
304 /** @defgroup RCC_APB1_Peripherals
305  * @{
306  */
307 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
308 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
309 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
310 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
311 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
312 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
313 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
314 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
315 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
316 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
317 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
318 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
319 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
320 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
321 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
322 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
323 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
324 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
325 #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
326 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
327 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
328 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
329 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
330 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00))
331 /**
332  * @}
333  */
334 
335 /** @defgroup RCC_APB2_Peripherals
336  * @{
337  */
338 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
339 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
340 #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
341 #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
342 #define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
343 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
344 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
345 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
346 #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
347 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
348 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
349 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
350 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
351 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
352 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00))
353 #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00))
354 /**
355  * @}
356  */
357 
358 /** @defgroup RCC_MCO1_Clock_Source_Prescaler
359  * @{
360  */
361 #define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
362 #define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
363 #define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
364 #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
365 #define RCC_MCO1Div_1 ((uint32_t)0x00000000)
366 #define RCC_MCO1Div_2 ((uint32_t)0x04000000)
367 #define RCC_MCO1Div_3 ((uint32_t)0x05000000)
368 #define RCC_MCO1Div_4 ((uint32_t)0x06000000)
369 #define RCC_MCO1Div_5 ((uint32_t)0x07000000)
370 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
371  ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
372 
373 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
374  ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
375  ((DIV) == RCC_MCO1Div_5))
376 /**
377  * @}
378  */
379 
380 /** @defgroup RCC_MCO2_Clock_Source_Prescaler
381  * @{
382  */
383 #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
384 #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
385 #define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
386 #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
387 #define RCC_MCO2Div_1 ((uint32_t)0x00000000)
388 #define RCC_MCO2Div_2 ((uint32_t)0x20000000)
389 #define RCC_MCO2Div_3 ((uint32_t)0x28000000)
390 #define RCC_MCO2Div_4 ((uint32_t)0x30000000)
391 #define RCC_MCO2Div_5 ((uint32_t)0x38000000)
392 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
393  ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
394 
395 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
396  ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
397  ((DIV) == RCC_MCO2Div_5))
398 /**
399  * @}
400  */
401 
402 /** @defgroup RCC_Flag
403  * @{
404  */
405 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
406 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
407 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
408 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
409 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
410 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
411 #define RCC_FLAG_BORRST ((uint8_t)0x79)
412 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
413 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
414 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
415 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
416 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
417 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
418 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
419  ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
420  ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
421  ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
422  ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
423  ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
424  ((FLAG) == RCC_FLAG_PLLI2SRDY))
425 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
426 /**
427  * @}
428  */
429 
430 /**
431  * @}
432  */
433 
434 /* Exported macro ------------------------------------------------------------*/
435 /* Exported functions --------------------------------------------------------*/
436 
437 /* Function used to set the RCC clock configuration to the default reset state */
438 void RCC_DeInit(void);
439 
440 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
441 void RCC_HSEConfig(uint8_t RCC_HSE);
442 ErrorStatus RCC_WaitForHSEStartUp(void);
443 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
444 void RCC_HSICmd(FunctionalState NewState);
445 void RCC_LSEConfig(uint8_t RCC_LSE);
446 void RCC_LSICmd(FunctionalState NewState);
447 
448 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
449 void RCC_PLLCmd(FunctionalState NewState);
450 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
451 void RCC_PLLI2SCmd(FunctionalState NewState);
452 
453 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
454 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
455 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
456 
457 /* System, AHB and APB busses clocks configuration functions ******************/
458 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
459 uint8_t RCC_GetSYSCLKSource(void);
460 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
461 void RCC_PCLK1Config(uint32_t RCC_HCLK);
462 void RCC_PCLK2Config(uint32_t RCC_HCLK);
463 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
464 
465 /* Peripheral clocks configuration functions **********************************/
466 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
467 void RCC_RTCCLKCmd(FunctionalState NewState);
468 void RCC_BackupResetCmd(FunctionalState NewState);
469 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
470 
471 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
472 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
473 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
474 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
475 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
476 
477 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
478 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
479 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
480 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
481 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
482 
483 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
484 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
485 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
486 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
487 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
488 
489 /* Interrupts and flags management functions **********************************/
490 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
491 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
492 void RCC_ClearFlag(void);
493 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
494 void RCC_ClearITPendingBit(uint8_t RCC_IT);
495 
496 #ifdef __cplusplus
497 }
498 #endif
499 
500 #endif /* __STM32F4xx_RCC_H */
501 
502 /**
503  * @}
504  */
505 
506 /**
507  * @}
508  */
509 
510 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
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