CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F4xx devices. More...

#include "cmsis/core_cm4.h"
#include "stm32/system_stm32f4xx.h"
#include <stdint.h>

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Data Structures
struct	ADC_TypeDef
	Analog to Digital Converter. More...

struct	CAN_TxMailBox_TypeDef
	Controller Area Network TxMailBox. More...

struct	CAN_FIFOMailBox_TypeDef
	Controller Area Network FIFOMailBox. More...

struct	CAN_FilterRegister_TypeDef
	Controller Area Network FilterRegister. More...

struct	CAN_TypeDef
	Controller Area Network. More...

struct	CRC_TypeDef
	CRC calculation unit. More...

struct	DAC_TypeDef
	Digital to Analog Converter. More...

struct	DBGMCU_TypeDef
	Debug MCU. More...

struct	DCMI_TypeDef
	DCMI. More...

struct	DMA_Stream_TypeDef
	DMA Controller. More...

struct	ETH_TypeDef
	Ethernet MAC. More...

struct	EXTI_TypeDef
	External Interrupt/Event Controller. More...

struct	FLASH_TypeDef
	FLASH Registers. More...

struct	FSMC_Bank1_TypeDef
	Flexible Static Memory Controller. More...

struct	FSMC_Bank1E_TypeDef
	Flexible Static Memory Controller Bank1E. More...

struct	FSMC_Bank2_TypeDef
	Flexible Static Memory Controller Bank2. More...

struct	FSMC_Bank3_TypeDef
	Flexible Static Memory Controller Bank3. More...

struct	FSMC_Bank4_TypeDef
	Flexible Static Memory Controller Bank4. More...

struct	GPIO_TypeDef
	General Purpose I/O. More...

struct	SYSCFG_TypeDef
	System configuration controller. More...

struct	I2C_TypeDef
	Inter-integrated Circuit Interface. More...

struct	IWDG_TypeDef
	Independent WATCHDOG. More...

struct	PWR_TypeDef
	Power Control. More...

struct	RCC_TypeDef
	Reset and Clock Control. More...

struct	RTC_TypeDef
	Real-Time Clock. More...

struct	SDIO_TypeDef
	SD host Interface. More...

struct	SPI_TypeDef
	Serial Peripheral Interface. More...

struct	TIM_TypeDef
	TIM. More...

struct	USART_TypeDef
	Universal Synchronous Asynchronous Receiver Transmitter. More...

struct	WWDG_TypeDef
	Window WATCHDOG. More...

struct	CRYP_TypeDef
	Crypto Processor. More...

struct	HASH_TypeDef
	HASH. More...

struct	RNG_TypeDef
	HASH. More...

Macros
#define	HSE_STARTUP_TIMEOUT
	Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers. More...

#define	HSI_VALUE

#define	__STM32F4XX_STDPERIPH_VERSION_MAIN
	STM32F4XX Standard Peripherals Library version number V1.0.0. More...

#define	__STM32F4XX_STDPERIPH_VERSION_SUB1

#define	__STM32F4XX_STDPERIPH_VERSION_SUB2

#define	__STM32F4XX_STDPERIPH_VERSION_RC

#define	__CM4_REV
	Configuration of the Cortex-M4 Processor and Core Peripherals. More...

#define	__MPU_PRESENT

#define	__NVIC_PRIO_BITS

#define	__Vendor_SysTickConfig

#define	FLASH_BASE

#define	CCMDATARAM_BASE

#define	SRAM1_BASE

#define	SRAM2_BASE

#define	PERIPH_BASE

#define	BKPSRAM_BASE

#define	FSMC_R_BASE

#define	CCMDATARAM_BB_BASE

#define	SRAM1_BB_BASE

#define	SRAM2_BB_BASE

#define	PERIPH_BB_BASE

#define	BKPSRAM_BB_BASE

#define	SRAM_BB_BASE

#define	AHB2PERIPH_BASE

#define	DAC_BASE

#define	TIM11_BASE

#define	ETH_DMA_BASE

#define	RNG_BASE

#define	ADC_SR_AWD

#define	ADC_SR_EOC

#define	ADC_SR_JEOC

#define	ADC_SR_JSTRT

#define	ADC_SR_STRT

#define	ADC_SR_OVR

#define	ADC_CR1_AWDCH

#define	ADC_CR1_AWDCH_0

#define	ADC_CR1_AWDCH_1

#define	ADC_CR1_AWDCH_2

#define	ADC_CR1_AWDCH_3

#define	ADC_CR1_AWDCH_4

#define	ADC_CR1_EOCIE

#define	ADC_CR1_AWDIE

#define	ADC_CR1_JEOCIE

#define	ADC_CR1_SCAN

#define	ADC_CR1_AWDSGL

#define	ADC_CR1_JAUTO

#define	ADC_CR1_DISCEN

#define	ADC_CR1_JDISCEN

#define	ADC_CR1_DISCNUM

#define	ADC_CR1_DISCNUM_0

#define	ADC_CR1_DISCNUM_1

#define	ADC_CR1_DISCNUM_2

#define	ADC_CR1_JAWDEN

#define	ADC_CR1_AWDEN

#define	ADC_CR1_RES

#define	ADC_CR1_RES_0

#define	ADC_CR1_RES_1

#define	ADC_CR1_OVRIE

#define	ADC_CR2_ADON

#define	ADC_CR2_CONT

#define	ADC_CR2_DMA

#define	ADC_CR2_DDS

#define	ADC_CR2_EOCS

#define	ADC_CR2_ALIGN

#define	ADC_CR2_JEXTSEL

#define	ADC_CR2_JEXTSEL_0

#define	ADC_CR2_JEXTSEL_1

#define	ADC_CR2_JEXTSEL_2

#define	ADC_CR2_JEXTSEL_3

#define	ADC_CR2_JEXTEN

#define	ADC_CR2_JEXTEN_0

#define	ADC_CR2_JEXTEN_1

#define	ADC_CR2_JSWSTART

#define	ADC_CR2_EXTSEL

#define	ADC_CR2_EXTSEL_0

#define	ADC_CR2_EXTSEL_1

#define	ADC_CR2_EXTSEL_2

#define	ADC_CR2_EXTSEL_3

#define	ADC_CR2_EXTEN

#define	ADC_CR2_EXTEN_0

#define	ADC_CR2_EXTEN_1

#define	ADC_CR2_SWSTART

#define	ADC_SMPR1_SMP10

#define	ADC_SMPR1_SMP10_0

#define	ADC_SMPR1_SMP10_1

#define	ADC_SMPR1_SMP10_2

#define	ADC_SMPR1_SMP11

#define	ADC_SMPR1_SMP11_0

#define	ADC_SMPR1_SMP11_1

#define	ADC_SMPR1_SMP11_2

#define	ADC_SMPR1_SMP12

#define	ADC_SMPR1_SMP12_0

#define	ADC_SMPR1_SMP12_1

#define	ADC_SMPR1_SMP12_2

#define	ADC_SMPR1_SMP13

#define	ADC_SMPR1_SMP13_0

#define	ADC_SMPR1_SMP13_1

#define	ADC_SMPR1_SMP13_2

#define	ADC_SMPR1_SMP14

#define	ADC_SMPR1_SMP14_0

#define	ADC_SMPR1_SMP14_1

#define	ADC_SMPR1_SMP14_2

#define	ADC_SMPR1_SMP15

#define	ADC_SMPR1_SMP15_0

#define	ADC_SMPR1_SMP15_1

#define	ADC_SMPR1_SMP15_2

#define	ADC_SMPR1_SMP16

#define	ADC_SMPR1_SMP16_0

#define	ADC_SMPR1_SMP16_1

#define	ADC_SMPR1_SMP16_2

#define	ADC_SMPR1_SMP17

#define	ADC_SMPR1_SMP17_0

#define	ADC_SMPR1_SMP17_1

#define	ADC_SMPR1_SMP17_2

#define	ADC_SMPR1_SMP18

#define	ADC_SMPR1_SMP18_0

#define	ADC_SMPR1_SMP18_1

#define	ADC_SMPR1_SMP18_2

#define	ADC_SMPR2_SMP0

#define	ADC_SMPR2_SMP0_0

#define	ADC_SMPR2_SMP0_1

#define	ADC_SMPR2_SMP0_2

#define	ADC_SMPR2_SMP1

#define	ADC_SMPR2_SMP1_0

#define	ADC_SMPR2_SMP1_1

#define	ADC_SMPR2_SMP1_2

#define	ADC_SMPR2_SMP2

#define	ADC_SMPR2_SMP2_0

#define	ADC_SMPR2_SMP2_1

#define	ADC_SMPR2_SMP2_2

#define	ADC_SMPR2_SMP3

#define	ADC_SMPR2_SMP3_0

#define	ADC_SMPR2_SMP3_1

#define	ADC_SMPR2_SMP3_2

#define	ADC_SMPR2_SMP4

#define	ADC_SMPR2_SMP4_0

#define	ADC_SMPR2_SMP4_1

#define	ADC_SMPR2_SMP4_2

#define	ADC_SMPR2_SMP5

#define	ADC_SMPR2_SMP5_0

#define	ADC_SMPR2_SMP5_1

#define	ADC_SMPR2_SMP5_2

#define	ADC_SMPR2_SMP6

#define	ADC_SMPR2_SMP6_0

#define	ADC_SMPR2_SMP6_1

#define	ADC_SMPR2_SMP6_2

#define	ADC_SMPR2_SMP7

#define	ADC_SMPR2_SMP7_0

#define	ADC_SMPR2_SMP7_1

#define	ADC_SMPR2_SMP7_2

#define	ADC_SMPR2_SMP8

#define	ADC_SMPR2_SMP8_0

#define	ADC_SMPR2_SMP8_1

#define	ADC_SMPR2_SMP8_2

#define	ADC_SMPR2_SMP9

#define	ADC_SMPR2_SMP9_0

#define	ADC_SMPR2_SMP9_1

#define	ADC_SMPR2_SMP9_2

#define	ADC_JOFR1_JOFFSET1

#define	ADC_JOFR2_JOFFSET2

#define	ADC_JOFR3_JOFFSET3

#define	ADC_JOFR4_JOFFSET4

#define	ADC_HTR_HT

#define	ADC_LTR_LT

#define	ADC_SQR1_SQ13

#define	ADC_SQR1_SQ13_0

#define	ADC_SQR1_SQ13_1

#define	ADC_SQR1_SQ13_2

#define	ADC_SQR1_SQ13_3

#define	ADC_SQR1_SQ13_4

#define	ADC_SQR1_SQ14

#define	ADC_SQR1_SQ14_0

#define	ADC_SQR1_SQ14_1

#define	ADC_SQR1_SQ14_2

#define	ADC_SQR1_SQ14_3

#define	ADC_SQR1_SQ14_4

#define	ADC_SQR1_SQ15

#define	ADC_SQR1_SQ15_0

#define	ADC_SQR1_SQ15_1

#define	ADC_SQR1_SQ15_2

#define	ADC_SQR1_SQ15_3

#define	ADC_SQR1_SQ15_4

#define	ADC_SQR1_SQ16

#define	ADC_SQR1_SQ16_0

#define	ADC_SQR1_SQ16_1

#define	ADC_SQR1_SQ16_2

#define	ADC_SQR1_SQ16_3

#define	ADC_SQR1_SQ16_4

#define	ADC_SQR1_L

#define	ADC_SQR1_L_0

#define	ADC_SQR1_L_1

#define	ADC_SQR1_L_2

#define	ADC_SQR1_L_3

#define	ADC_SQR2_SQ7

#define	ADC_SQR2_SQ7_0

#define	ADC_SQR2_SQ7_1

#define	ADC_SQR2_SQ7_2

#define	ADC_SQR2_SQ7_3

#define	ADC_SQR2_SQ7_4

#define	ADC_SQR2_SQ8

#define	ADC_SQR2_SQ8_0

#define	ADC_SQR2_SQ8_1

#define	ADC_SQR2_SQ8_2

#define	ADC_SQR2_SQ8_3

#define	ADC_SQR2_SQ8_4

#define	ADC_SQR2_SQ9

#define	ADC_SQR2_SQ9_0

#define	ADC_SQR2_SQ9_1

#define	ADC_SQR2_SQ9_2

#define	ADC_SQR2_SQ9_3

#define	ADC_SQR2_SQ9_4

#define	ADC_SQR2_SQ10

#define	ADC_SQR2_SQ10_0

#define	ADC_SQR2_SQ10_1

#define	ADC_SQR2_SQ10_2

#define	ADC_SQR2_SQ10_3

#define	ADC_SQR2_SQ10_4

#define	ADC_SQR2_SQ11

#define	ADC_SQR2_SQ11_0

#define	ADC_SQR2_SQ11_1

#define	ADC_SQR2_SQ11_2

#define	ADC_SQR2_SQ11_3

#define	ADC_SQR2_SQ11_4

#define	ADC_SQR2_SQ12

#define	ADC_SQR2_SQ12_0

#define	ADC_SQR2_SQ12_1

#define	ADC_SQR2_SQ12_2

#define	ADC_SQR2_SQ12_3

#define	ADC_SQR2_SQ12_4

#define	ADC_SQR3_SQ1

#define	ADC_SQR3_SQ1_0

#define	ADC_SQR3_SQ1_1

#define	ADC_SQR3_SQ1_2

#define	ADC_SQR3_SQ1_3

#define	ADC_SQR3_SQ1_4

#define	ADC_SQR3_SQ2

#define	ADC_SQR3_SQ2_0

#define	ADC_SQR3_SQ2_1

#define	ADC_SQR3_SQ2_2

#define	ADC_SQR3_SQ2_3

#define	ADC_SQR3_SQ2_4

#define	ADC_SQR3_SQ3

#define	ADC_SQR3_SQ3_0

#define	ADC_SQR3_SQ3_1

#define	ADC_SQR3_SQ3_2

#define	ADC_SQR3_SQ3_3

#define	ADC_SQR3_SQ3_4

#define	ADC_SQR3_SQ4

#define	ADC_SQR3_SQ4_0

#define	ADC_SQR3_SQ4_1

#define	ADC_SQR3_SQ4_2

#define	ADC_SQR3_SQ4_3

#define	ADC_SQR3_SQ4_4

#define	ADC_SQR3_SQ5

#define	ADC_SQR3_SQ5_0

#define	ADC_SQR3_SQ5_1

#define	ADC_SQR3_SQ5_2

#define	ADC_SQR3_SQ5_3

#define	ADC_SQR3_SQ5_4

#define	ADC_SQR3_SQ6

#define	ADC_SQR3_SQ6_0

#define	ADC_SQR3_SQ6_1

#define	ADC_SQR3_SQ6_2

#define	ADC_SQR3_SQ6_3

#define	ADC_SQR3_SQ6_4

#define	ADC_JSQR_JSQ1

#define	ADC_JSQR_JSQ1_0

#define	ADC_JSQR_JSQ1_1

#define	ADC_JSQR_JSQ1_2

#define	ADC_JSQR_JSQ1_3

#define	ADC_JSQR_JSQ1_4

#define	ADC_JSQR_JSQ2

#define	ADC_JSQR_JSQ2_0

#define	ADC_JSQR_JSQ2_1

#define	ADC_JSQR_JSQ2_2

#define	ADC_JSQR_JSQ2_3

#define	ADC_JSQR_JSQ2_4

#define	ADC_JSQR_JSQ3

#define	ADC_JSQR_JSQ3_0

#define	ADC_JSQR_JSQ3_1

#define	ADC_JSQR_JSQ3_2

#define	ADC_JSQR_JSQ3_3

#define	ADC_JSQR_JSQ3_4

#define	ADC_JSQR_JSQ4

#define	ADC_JSQR_JSQ4_0

#define	ADC_JSQR_JSQ4_1

#define	ADC_JSQR_JSQ4_2

#define	ADC_JSQR_JSQ4_3

#define	ADC_JSQR_JSQ4_4

#define	ADC_JSQR_JL

#define	ADC_JSQR_JL_0

#define	ADC_JSQR_JL_1

#define	ADC_JDR1_JDATA

#define	ADC_JDR2_JDATA

#define	ADC_JDR3_JDATA

#define	ADC_JDR4_JDATA

#define	ADC_DR_DATA

#define	ADC_DR_ADC2DATA

#define	ADC_CSR_AWD1

#define	ADC_CSR_EOC1

#define	ADC_CSR_JEOC1

#define	ADC_CSR_JSTRT1

#define	ADC_CSR_STRT1

#define	ADC_CSR_DOVR1

#define	ADC_CSR_AWD2

#define	ADC_CSR_EOC2

#define	ADC_CSR_JEOC2

#define	ADC_CSR_JSTRT2

#define	ADC_CSR_STRT2

#define	ADC_CSR_DOVR2

#define	ADC_CSR_AWD3

#define	ADC_CSR_EOC3

#define	ADC_CSR_JEOC3

#define	ADC_CSR_JSTRT3

#define	ADC_CSR_STRT3

#define	ADC_CSR_DOVR3

#define	ADC_CCR_MULTI

#define	ADC_CCR_MULTI_0

#define	ADC_CCR_MULTI_1

#define	ADC_CCR_MULTI_2

#define	ADC_CCR_MULTI_3

#define	ADC_CCR_MULTI_4

#define	ADC_CCR_DELAY

#define	ADC_CCR_DELAY_0

#define	ADC_CCR_DELAY_1

#define	ADC_CCR_DELAY_2

#define	ADC_CCR_DELAY_3

#define	ADC_CCR_DDS

#define	ADC_CCR_DMA

#define	ADC_CCR_DMA_0

#define	ADC_CCR_DMA_1

#define	ADC_CCR_ADCPRE

#define	ADC_CCR_ADCPRE_0

#define	ADC_CCR_ADCPRE_1

#define	ADC_CCR_VBATE

#define	ADC_CCR_TSVREFE

#define	ADC_CDR_DATA1

#define	ADC_CDR_DATA2

#define	CAN_MCR_INRQ

#define	CAN_MCR_SLEEP

#define	CAN_MCR_TXFP

#define	CAN_MCR_RFLM

#define	CAN_MCR_NART

#define	CAN_MCR_AWUM

#define	CAN_MCR_ABOM

#define	CAN_MCR_TTCM

#define	CAN_MCR_RESET

#define	CAN_MSR_INAK

#define	CAN_MSR_SLAK

#define	CAN_MSR_ERRI

#define	CAN_MSR_WKUI

#define	CAN_MSR_SLAKI

#define	CAN_MSR_TXM

#define	CAN_MSR_RXM

#define	CAN_MSR_SAMP

#define	CAN_MSR_RX

#define	CAN_TSR_RQCP0

#define	CAN_TSR_TXOK0

#define	CAN_TSR_ALST0

#define	CAN_TSR_TERR0

#define	CAN_TSR_ABRQ0

#define	CAN_TSR_RQCP1

#define	CAN_TSR_TXOK1

#define	CAN_TSR_ALST1

#define	CAN_TSR_TERR1

#define	CAN_TSR_ABRQ1

#define	CAN_TSR_RQCP2

#define	CAN_TSR_TXOK2

#define	CAN_TSR_ALST2

#define	CAN_TSR_TERR2

#define	CAN_TSR_ABRQ2

#define	CAN_TSR_CODE

#define	CAN_TSR_TME

#define	CAN_TSR_TME0

#define	CAN_TSR_TME1

#define	CAN_TSR_TME2

#define	CAN_TSR_LOW

#define	CAN_TSR_LOW0

#define	CAN_TSR_LOW1

#define	CAN_TSR_LOW2

#define	CAN_RF0R_FMP0

#define	CAN_RF0R_FULL0

#define	CAN_RF0R_FOVR0

#define	CAN_RF0R_RFOM0

#define	CAN_RF1R_FMP1

#define	CAN_RF1R_FULL1

#define	CAN_RF1R_FOVR1

#define	CAN_RF1R_RFOM1

#define	CAN_IER_TMEIE

#define	CAN_IER_FMPIE0

#define	CAN_IER_FFIE0

#define	CAN_IER_FOVIE0

#define	CAN_IER_FMPIE1

#define	CAN_IER_FFIE1

#define	CAN_IER_FOVIE1

#define	CAN_IER_EWGIE

#define	CAN_IER_EPVIE

#define	CAN_IER_BOFIE

#define	CAN_IER_LECIE

#define	CAN_IER_ERRIE

#define	CAN_IER_WKUIE

#define	CAN_IER_SLKIE

#define	CAN_ESR_EWGF

#define	CAN_ESR_EPVF

#define	CAN_ESR_BOFF

#define	CAN_ESR_LEC

#define	CAN_ESR_LEC_0

#define	CAN_ESR_LEC_1

#define	CAN_ESR_LEC_2

#define	CAN_ESR_TEC

#define	CAN_ESR_REC

#define	CAN_BTR_BRP

#define	CAN_BTR_TS1

#define	CAN_BTR_TS2

#define	CAN_BTR_SJW

#define	CAN_BTR_LBKM

#define	CAN_BTR_SILM

#define	CAN_TI0R_TXRQ

#define	CAN_TI0R_RTR

#define	CAN_TI0R_IDE

#define	CAN_TI0R_EXID

#define	CAN_TI0R_STID

#define	CAN_TDT0R_DLC

#define	CAN_TDT0R_TGT

#define	CAN_TDT0R_TIME

#define	CAN_TDL0R_DATA0

#define	CAN_TDL0R_DATA1

#define	CAN_TDL0R_DATA2

#define	CAN_TDL0R_DATA3

#define	CAN_TDH0R_DATA4

#define	CAN_TDH0R_DATA5

#define	CAN_TDH0R_DATA6

#define	CAN_TDH0R_DATA7

#define	CAN_TI1R_TXRQ

#define	CAN_TI1R_RTR

#define	CAN_TI1R_IDE

#define	CAN_TI1R_EXID

#define	CAN_TI1R_STID

#define	CAN_TDT1R_DLC

#define	CAN_TDT1R_TGT

#define	CAN_TDT1R_TIME

#define	CAN_TDL1R_DATA0

#define	CAN_TDL1R_DATA1

#define	CAN_TDL1R_DATA2

#define	CAN_TDL1R_DATA3

#define	CAN_TDH1R_DATA4

#define	CAN_TDH1R_DATA5

#define	CAN_TDH1R_DATA6

#define	CAN_TDH1R_DATA7

#define	CAN_TI2R_TXRQ

#define	CAN_TI2R_RTR

#define	CAN_TI2R_IDE

#define	CAN_TI2R_EXID

#define	CAN_TI2R_STID

#define	CAN_TDT2R_DLC

#define	CAN_TDT2R_TGT

#define	CAN_TDT2R_TIME

#define	CAN_TDL2R_DATA0

#define	CAN_TDL2R_DATA1

#define	CAN_TDL2R_DATA2

#define	CAN_TDL2R_DATA3

#define	CAN_TDH2R_DATA4

#define	CAN_TDH2R_DATA5

#define	CAN_TDH2R_DATA6

#define	CAN_TDH2R_DATA7

#define	CAN_RI0R_RTR

#define	CAN_RI0R_IDE

#define	CAN_RI0R_EXID

#define	CAN_RI0R_STID

#define	CAN_RDT0R_DLC

#define	CAN_RDT0R_FMI

#define	CAN_RDT0R_TIME

#define	CAN_RDL0R_DATA0

#define	CAN_RDL0R_DATA1

#define	CAN_RDL0R_DATA2

#define	CAN_RDL0R_DATA3

#define	CAN_RDH0R_DATA4

#define	CAN_RDH0R_DATA5

#define	CAN_RDH0R_DATA6

#define	CAN_RDH0R_DATA7

#define	CAN_RI1R_RTR

#define	CAN_RI1R_IDE

#define	CAN_RI1R_EXID

#define	CAN_RI1R_STID

#define	CAN_RDT1R_DLC

#define	CAN_RDT1R_FMI

#define	CAN_RDT1R_TIME

#define	CAN_RDL1R_DATA0

#define	CAN_RDL1R_DATA1

#define	CAN_RDL1R_DATA2

#define	CAN_RDL1R_DATA3

#define	CAN_RDH1R_DATA4

#define	CAN_RDH1R_DATA5

#define	CAN_RDH1R_DATA6

#define	CAN_RDH1R_DATA7

#define	CAN_FMR_FINIT

#define	CAN_FM1R_FBM

#define	CAN_FM1R_FBM0

#define	CAN_FM1R_FBM1

#define	CAN_FM1R_FBM2

#define	CAN_FM1R_FBM3

#define	CAN_FM1R_FBM4

#define	CAN_FM1R_FBM5

#define	CAN_FM1R_FBM6

#define	CAN_FM1R_FBM7

#define	CAN_FM1R_FBM8

#define	CAN_FM1R_FBM9

#define	CAN_FM1R_FBM10

#define	CAN_FM1R_FBM11

#define	CAN_FM1R_FBM12

#define	CAN_FM1R_FBM13

#define	CAN_FS1R_FSC

#define	CAN_FS1R_FSC0

#define	CAN_FS1R_FSC1

#define	CAN_FS1R_FSC2

#define	CAN_FS1R_FSC3

#define	CAN_FS1R_FSC4

#define	CAN_FS1R_FSC5

#define	CAN_FS1R_FSC6

#define	CAN_FS1R_FSC7

#define	CAN_FS1R_FSC8

#define	CAN_FS1R_FSC9

#define	CAN_FS1R_FSC10

#define	CAN_FS1R_FSC11

#define	CAN_FS1R_FSC12

#define	CAN_FS1R_FSC13

#define	CAN_FFA1R_FFA

#define	CAN_FFA1R_FFA0

#define	CAN_FFA1R_FFA1

#define	CAN_FFA1R_FFA2

#define	CAN_FFA1R_FFA3

#define	CAN_FFA1R_FFA4

#define	CAN_FFA1R_FFA5

#define	CAN_FFA1R_FFA6

#define	CAN_FFA1R_FFA7

#define	CAN_FFA1R_FFA8

#define	CAN_FFA1R_FFA9

#define	CAN_FFA1R_FFA10

#define	CAN_FFA1R_FFA11

#define	CAN_FFA1R_FFA12

#define	CAN_FFA1R_FFA13

#define	CAN_FA1R_FACT

#define	CAN_FA1R_FACT0

#define	CAN_FA1R_FACT1

#define	CAN_FA1R_FACT2

#define	CAN_FA1R_FACT3

#define	CAN_FA1R_FACT4

#define	CAN_FA1R_FACT5

#define	CAN_FA1R_FACT6

#define	CAN_FA1R_FACT7

#define	CAN_FA1R_FACT8

#define	CAN_FA1R_FACT9

#define	CAN_FA1R_FACT10

#define	CAN_FA1R_FACT11

#define	CAN_FA1R_FACT12

#define	CAN_FA1R_FACT13

#define	CAN_F0R1_FB0

#define	CAN_F0R1_FB1

#define	CAN_F0R1_FB2

#define	CAN_F0R1_FB3

#define	CAN_F0R1_FB4

#define	CAN_F0R1_FB5

#define	CAN_F0R1_FB6

#define	CAN_F0R1_FB7

#define	CAN_F0R1_FB8

#define	CAN_F0R1_FB9

#define	CAN_F0R1_FB10

#define	CAN_F0R1_FB11

#define	CAN_F0R1_FB12

#define	CAN_F0R1_FB13

#define	CAN_F0R1_FB14

#define	CAN_F0R1_FB15

#define	CAN_F0R1_FB16

#define	CAN_F0R1_FB17

#define	CAN_F0R1_FB18

#define	CAN_F0R1_FB19

#define	CAN_F0R1_FB20

#define	CAN_F0R1_FB21

#define	CAN_F0R1_FB22

#define	CAN_F0R1_FB23

#define	CAN_F0R1_FB24

#define	CAN_F0R1_FB25

#define	CAN_F0R1_FB26

#define	CAN_F0R1_FB27

#define	CAN_F0R1_FB28

#define	CAN_F0R1_FB29

#define	CAN_F0R1_FB30

#define	CAN_F0R1_FB31

#define	CAN_F1R1_FB0

#define	CAN_F1R1_FB1

#define	CAN_F1R1_FB2

#define	CAN_F1R1_FB3

#define	CAN_F1R1_FB4

#define	CAN_F1R1_FB5

#define	CAN_F1R1_FB6

#define	CAN_F1R1_FB7

#define	CAN_F1R1_FB8

#define	CAN_F1R1_FB9

#define	CAN_F1R1_FB10

#define	CAN_F1R1_FB11

#define	CAN_F1R1_FB12

#define	CAN_F1R1_FB13

#define	CAN_F1R1_FB14

#define	CAN_F1R1_FB15

#define	CAN_F1R1_FB16

#define	CAN_F1R1_FB17

#define	CAN_F1R1_FB18

#define	CAN_F1R1_FB19

#define	CAN_F1R1_FB20

#define	CAN_F1R1_FB21

#define	CAN_F1R1_FB22

#define	CAN_F1R1_FB23

#define	CAN_F1R1_FB24

#define	CAN_F1R1_FB25

#define	CAN_F1R1_FB26

#define	CAN_F1R1_FB27

#define	CAN_F1R1_FB28

#define	CAN_F1R1_FB29

#define	CAN_F1R1_FB30

#define	CAN_F1R1_FB31

#define	CAN_F2R1_FB0

#define	CAN_F2R1_FB1

#define	CAN_F2R1_FB2

#define	CAN_F2R1_FB3

#define	CAN_F2R1_FB4

#define	CAN_F2R1_FB5

#define	CAN_F2R1_FB6

#define	CAN_F2R1_FB7

#define	CAN_F2R1_FB8

#define	CAN_F2R1_FB9

#define	CAN_F2R1_FB10

#define	CAN_F2R1_FB11

#define	CAN_F2R1_FB12

#define	CAN_F2R1_FB13

#define	CAN_F2R1_FB14

#define	CAN_F2R1_FB15

#define	CAN_F2R1_FB16

#define	CAN_F2R1_FB17

#define	CAN_F2R1_FB18

#define	CAN_F2R1_FB19

#define	CAN_F2R1_FB20

#define	CAN_F2R1_FB21

#define	CAN_F2R1_FB22

#define	CAN_F2R1_FB23

#define	CAN_F2R1_FB24

#define	CAN_F2R1_FB25

#define	CAN_F2R1_FB26

#define	CAN_F2R1_FB27

#define	CAN_F2R1_FB28

#define	CAN_F2R1_FB29

#define	CAN_F2R1_FB30

#define	CAN_F2R1_FB31

#define	CAN_F3R1_FB0

#define	CAN_F3R1_FB1

#define	CAN_F3R1_FB2

#define	CAN_F3R1_FB3

#define	CAN_F3R1_FB4

#define	CAN_F3R1_FB5

#define	CAN_F3R1_FB6

#define	CAN_F3R1_FB7

#define	CAN_F3R1_FB8

#define	CAN_F3R1_FB9

#define	CAN_F3R1_FB10

#define	CAN_F3R1_FB11

#define	CAN_F3R1_FB12

#define	CAN_F3R1_FB13

#define	CAN_F3R1_FB14

#define	CAN_F3R1_FB15

#define	CAN_F3R1_FB16

#define	CAN_F3R1_FB17

#define	CAN_F3R1_FB18

#define	CAN_F3R1_FB19

#define	CAN_F3R1_FB20

#define	CAN_F3R1_FB21

#define	CAN_F3R1_FB22

#define	CAN_F3R1_FB23

#define	CAN_F3R1_FB24

#define	CAN_F3R1_FB25

#define	CAN_F3R1_FB26

#define	CAN_F3R1_FB27

#define	CAN_F3R1_FB28

#define	CAN_F3R1_FB29

#define	CAN_F3R1_FB30

#define	CAN_F3R1_FB31

#define	CAN_F4R1_FB0

#define	CAN_F4R1_FB1

#define	CAN_F4R1_FB2

#define	CAN_F4R1_FB3

#define	CAN_F4R1_FB4

#define	CAN_F4R1_FB5

#define	CAN_F4R1_FB6

#define	CAN_F4R1_FB7

#define	CAN_F4R1_FB8

#define	CAN_F4R1_FB9

#define	CAN_F4R1_FB10

#define	CAN_F4R1_FB11

#define	CAN_F4R1_FB12

#define	CAN_F4R1_FB13

#define	CAN_F4R1_FB14

#define	CAN_F4R1_FB15

#define	CAN_F4R1_FB16

#define	CAN_F4R1_FB17

#define	CAN_F4R1_FB18

#define	CAN_F4R1_FB19

#define	CAN_F4R1_FB20

#define	CAN_F4R1_FB21

#define	CAN_F4R1_FB22

#define	CAN_F4R1_FB23

#define	CAN_F4R1_FB24

#define	CAN_F4R1_FB25

#define	CAN_F4R1_FB26

#define	CAN_F4R1_FB27

#define	CAN_F4R1_FB28

#define	CAN_F4R1_FB29

#define	CAN_F4R1_FB30

#define	CAN_F4R1_FB31

#define	CAN_F5R1_FB0

#define	CAN_F5R1_FB1

#define	CAN_F5R1_FB2

#define	CAN_F5R1_FB3

#define	CAN_F5R1_FB4

#define	CAN_F5R1_FB5

#define	CAN_F5R1_FB6

#define	CAN_F5R1_FB7

#define	CAN_F5R1_FB8

#define	CAN_F5R1_FB9

#define	CAN_F5R1_FB10

#define	CAN_F5R1_FB11

#define	CAN_F5R1_FB12

#define	CAN_F5R1_FB13

#define	CAN_F5R1_FB14

#define	CAN_F5R1_FB15

#define	CAN_F5R1_FB16

#define	CAN_F5R1_FB17

#define	CAN_F5R1_FB18

#define	CAN_F5R1_FB19

#define	CAN_F5R1_FB20

#define	CAN_F5R1_FB21

#define	CAN_F5R1_FB22

#define	CAN_F5R1_FB23

#define	CAN_F5R1_FB24

#define	CAN_F5R1_FB25

#define	CAN_F5R1_FB26

#define	CAN_F5R1_FB27

#define	CAN_F5R1_FB28

#define	CAN_F5R1_FB29

#define	CAN_F5R1_FB30

#define	CAN_F5R1_FB31

#define	CAN_F6R1_FB0

#define	CAN_F6R1_FB1

#define	CAN_F6R1_FB2

#define	CAN_F6R1_FB3

#define	CAN_F6R1_FB4

#define	CAN_F6R1_FB5

#define	CAN_F6R1_FB6

#define	CAN_F6R1_FB7

#define	CAN_F6R1_FB8

#define	CAN_F6R1_FB9

#define	CAN_F6R1_FB10

#define	CAN_F6R1_FB11

#define	CAN_F6R1_FB12

#define	CAN_F6R1_FB13

#define	CAN_F6R1_FB14

#define	CAN_F6R1_FB15

#define	CAN_F6R1_FB16

#define	CAN_F6R1_FB17

#define	CAN_F6R1_FB18

#define	CAN_F6R1_FB19

#define	CAN_F6R1_FB20

#define	CAN_F6R1_FB21

#define	CAN_F6R1_FB22

#define	CAN_F6R1_FB23

#define	CAN_F6R1_FB24

#define	CAN_F6R1_FB25

#define	CAN_F6R1_FB26

#define	CAN_F6R1_FB27

#define	CAN_F6R1_FB28

#define	CAN_F6R1_FB29

#define	CAN_F6R1_FB30

#define	CAN_F6R1_FB31

#define	CAN_F7R1_FB0

#define	CAN_F7R1_FB1

#define	CAN_F7R1_FB2

#define	CAN_F7R1_FB3

#define	CAN_F7R1_FB4

#define	CAN_F7R1_FB5

#define	CAN_F7R1_FB6

#define	CAN_F7R1_FB7

#define	CAN_F7R1_FB8

#define	CAN_F7R1_FB9

#define	CAN_F7R1_FB10

#define	CAN_F7R1_FB11

#define	CAN_F7R1_FB12

#define	CAN_F7R1_FB13

#define	CAN_F7R1_FB14

#define	CAN_F7R1_FB15

#define	CAN_F7R1_FB16

#define	CAN_F7R1_FB17

#define	CAN_F7R1_FB18

#define	CAN_F7R1_FB19

#define	CAN_F7R1_FB20

#define	CAN_F7R1_FB21

#define	CAN_F7R1_FB22

#define	CAN_F7R1_FB23

#define	CAN_F7R1_FB24

#define	CAN_F7R1_FB25

#define	CAN_F7R1_FB26

#define	CAN_F7R1_FB27

#define	CAN_F7R1_FB28

#define	CAN_F7R1_FB29

#define	CAN_F7R1_FB30

#define	CAN_F7R1_FB31

#define	CAN_F8R1_FB0

#define	CAN_F8R1_FB1

#define	CAN_F8R1_FB2

#define	CAN_F8R1_FB3

#define	CAN_F8R1_FB4

#define	CAN_F8R1_FB5

#define	CAN_F8R1_FB6

#define	CAN_F8R1_FB7

#define	CAN_F8R1_FB8

#define	CAN_F8R1_FB9

#define	CAN_F8R1_FB10

#define	CAN_F8R1_FB11

#define	CAN_F8R1_FB12

#define	CAN_F8R1_FB13

#define	CAN_F8R1_FB14

#define	CAN_F8R1_FB15

#define	CAN_F8R1_FB16

#define	CAN_F8R1_FB17

#define	CAN_F8R1_FB18

#define	CAN_F8R1_FB19

#define	CAN_F8R1_FB20

#define	CAN_F8R1_FB21

#define	CAN_F8R1_FB22

#define	CAN_F8R1_FB23

#define	CAN_F8R1_FB24

#define	CAN_F8R1_FB25

#define	CAN_F8R1_FB26

#define	CAN_F8R1_FB27

#define	CAN_F8R1_FB28

#define	CAN_F8R1_FB29

#define	CAN_F8R1_FB30

#define	CAN_F8R1_FB31

#define	CAN_F9R1_FB0

#define	CAN_F9R1_FB1

#define	CAN_F9R1_FB2

#define	CAN_F9R1_FB3

#define	CAN_F9R1_FB4

#define	CAN_F9R1_FB5

#define	CAN_F9R1_FB6

#define	CAN_F9R1_FB7

#define	CAN_F9R1_FB8

#define	CAN_F9R1_FB9

#define	CAN_F9R1_FB10

#define	CAN_F9R1_FB11

#define	CAN_F9R1_FB12

#define	CAN_F9R1_FB13

#define	CAN_F9R1_FB14

#define	CAN_F9R1_FB15

#define	CAN_F9R1_FB16

#define	CAN_F9R1_FB17

#define	CAN_F9R1_FB18

#define	CAN_F9R1_FB19

#define	CAN_F9R1_FB20

#define	CAN_F9R1_FB21

#define	CAN_F9R1_FB22

#define	CAN_F9R1_FB23

#define	CAN_F9R1_FB24

#define	CAN_F9R1_FB25

#define	CAN_F9R1_FB26

#define	CAN_F9R1_FB27

#define	CAN_F9R1_FB28

#define	CAN_F9R1_FB29

#define	CAN_F9R1_FB30

#define	CAN_F9R1_FB31

#define	CAN_F10R1_FB0

#define	CAN_F10R1_FB1

#define	CAN_F10R1_FB2

#define	CAN_F10R1_FB3

#define	CAN_F10R1_FB4

#define	CAN_F10R1_FB5

#define	CAN_F10R1_FB6

#define	CAN_F10R1_FB7

#define	CAN_F10R1_FB8

#define	CAN_F10R1_FB9

#define	CAN_F10R1_FB10

#define	CAN_F10R1_FB11

#define	CAN_F10R1_FB12

#define	CAN_F10R1_FB13

#define	CAN_F10R1_FB14

#define	CAN_F10R1_FB15

#define	CAN_F10R1_FB16

#define	CAN_F10R1_FB17

#define	CAN_F10R1_FB18

#define	CAN_F10R1_FB19

#define	CAN_F10R1_FB20

#define	CAN_F10R1_FB21

#define	CAN_F10R1_FB22

#define	CAN_F10R1_FB23

#define	CAN_F10R1_FB24

#define	CAN_F10R1_FB25

#define	CAN_F10R1_FB26

#define	CAN_F10R1_FB27

#define	CAN_F10R1_FB28

#define	CAN_F10R1_FB29

#define	CAN_F10R1_FB30

#define	CAN_F10R1_FB31

#define	CAN_F11R1_FB0

#define	CAN_F11R1_FB1

#define	CAN_F11R1_FB2

#define	CAN_F11R1_FB3

#define	CAN_F11R1_FB4

#define	CAN_F11R1_FB5

#define	CAN_F11R1_FB6

#define	CAN_F11R1_FB7

#define	CAN_F11R1_FB8

#define	CAN_F11R1_FB9

#define	CAN_F11R1_FB10

#define	CAN_F11R1_FB11

#define	CAN_F11R1_FB12

#define	CAN_F11R1_FB13

#define	CAN_F11R1_FB14

#define	CAN_F11R1_FB15

#define	CAN_F11R1_FB16

#define	CAN_F11R1_FB17

#define	CAN_F11R1_FB18

#define	CAN_F11R1_FB19

#define	CAN_F11R1_FB20

#define	CAN_F11R1_FB21

#define	CAN_F11R1_FB22

#define	CAN_F11R1_FB23

#define	CAN_F11R1_FB24

#define	CAN_F11R1_FB25

#define	CAN_F11R1_FB26

#define	CAN_F11R1_FB27

#define	CAN_F11R1_FB28

#define	CAN_F11R1_FB29

#define	CAN_F11R1_FB30

#define	CAN_F11R1_FB31

#define	CAN_F12R1_FB0

#define	CAN_F12R1_FB1

#define	CAN_F12R1_FB2

#define	CAN_F12R1_FB3

#define	CAN_F12R1_FB4

#define	CAN_F12R1_FB5

#define	CAN_F12R1_FB6

#define	CAN_F12R1_FB7

#define	CAN_F12R1_FB8

#define	CAN_F12R1_FB9

#define	CAN_F12R1_FB10

#define	CAN_F12R1_FB11

#define	CAN_F12R1_FB12

#define	CAN_F12R1_FB13

#define	CAN_F12R1_FB14

#define	CAN_F12R1_FB15

#define	CAN_F12R1_FB16

#define	CAN_F12R1_FB17

#define	CAN_F12R1_FB18

#define	CAN_F12R1_FB19

#define	CAN_F12R1_FB20

#define	CAN_F12R1_FB21

#define	CAN_F12R1_FB22

#define	CAN_F12R1_FB23

#define	CAN_F12R1_FB24

#define	CAN_F12R1_FB25

#define	CAN_F12R1_FB26

#define	CAN_F12R1_FB27

#define	CAN_F12R1_FB28

#define	CAN_F12R1_FB29

#define	CAN_F12R1_FB30

#define	CAN_F12R1_FB31

#define	CAN_F13R1_FB0

#define	CAN_F13R1_FB1

#define	CAN_F13R1_FB2

#define	CAN_F13R1_FB3

#define	CAN_F13R1_FB4

#define	CAN_F13R1_FB5

#define	CAN_F13R1_FB6

#define	CAN_F13R1_FB7

#define	CAN_F13R1_FB8

#define	CAN_F13R1_FB9

#define	CAN_F13R1_FB10

#define	CAN_F13R1_FB11

#define	CAN_F13R1_FB12

#define	CAN_F13R1_FB13

#define	CAN_F13R1_FB14

#define	CAN_F13R1_FB15

#define	CAN_F13R1_FB16

#define	CAN_F13R1_FB17

#define	CAN_F13R1_FB18

#define	CAN_F13R1_FB19

#define	CAN_F13R1_FB20

#define	CAN_F13R1_FB21

#define	CAN_F13R1_FB22

#define	CAN_F13R1_FB23

#define	CAN_F13R1_FB24

#define	CAN_F13R1_FB25

#define	CAN_F13R1_FB26

#define	CAN_F13R1_FB27

#define	CAN_F13R1_FB28

#define	CAN_F13R1_FB29

#define	CAN_F13R1_FB30

#define	CAN_F13R1_FB31

#define	CAN_F0R2_FB0

#define	CAN_F0R2_FB1

#define	CAN_F0R2_FB2

#define	CAN_F0R2_FB3

#define	CAN_F0R2_FB4

#define	CAN_F0R2_FB5

#define	CAN_F0R2_FB6

#define	CAN_F0R2_FB7

#define	CAN_F0R2_FB8

#define	CAN_F0R2_FB9

#define	CAN_F0R2_FB10

#define	CAN_F0R2_FB11

#define	CAN_F0R2_FB12

#define	CAN_F0R2_FB13

#define	CAN_F0R2_FB14

#define	CAN_F0R2_FB15

#define	CAN_F0R2_FB16

#define	CAN_F0R2_FB17

#define	CAN_F0R2_FB18

#define	CAN_F0R2_FB19

#define	CAN_F0R2_FB20

#define	CAN_F0R2_FB21

#define	CAN_F0R2_FB22

#define	CAN_F0R2_FB23

#define	CAN_F0R2_FB24

#define	CAN_F0R2_FB25

#define	CAN_F0R2_FB26

#define	CAN_F0R2_FB27

#define	CAN_F0R2_FB28

#define	CAN_F0R2_FB29

#define	CAN_F0R2_FB30

#define	CAN_F0R2_FB31

#define	CAN_F1R2_FB0

#define	CAN_F1R2_FB1

#define	CAN_F1R2_FB2

#define	CAN_F1R2_FB3

#define	CAN_F1R2_FB4

#define	CAN_F1R2_FB5

#define	CAN_F1R2_FB6

#define	CAN_F1R2_FB7

#define	CAN_F1R2_FB8

#define	CAN_F1R2_FB9

#define	CAN_F1R2_FB10

#define	CAN_F1R2_FB11

#define	CAN_F1R2_FB12

#define	CAN_F1R2_FB13

#define	CAN_F1R2_FB14

#define	CAN_F1R2_FB15

#define	CAN_F1R2_FB16

#define	CAN_F1R2_FB17

#define	CAN_F1R2_FB18

#define	CAN_F1R2_FB19

#define	CAN_F1R2_FB20

#define	CAN_F1R2_FB21

#define	CAN_F1R2_FB22

#define	CAN_F1R2_FB23

#define	CAN_F1R2_FB24

#define	CAN_F1R2_FB25

#define	CAN_F1R2_FB26

#define	CAN_F1R2_FB27

#define	CAN_F1R2_FB28

#define	CAN_F1R2_FB29

#define	CAN_F1R2_FB30

#define	CAN_F1R2_FB31

#define	CAN_F2R2_FB0

#define	CAN_F2R2_FB1

#define	CAN_F2R2_FB2

#define	CAN_F2R2_FB3

#define	CAN_F2R2_FB4

#define	CAN_F2R2_FB5

#define	CAN_F2R2_FB6

#define	CAN_F2R2_FB7

#define	CAN_F2R2_FB8

#define	CAN_F2R2_FB9

#define	CAN_F2R2_FB10

#define	CAN_F2R2_FB11

#define	CAN_F2R2_FB12

#define	CAN_F2R2_FB13

#define	CAN_F2R2_FB14

#define	CAN_F2R2_FB15

#define	CAN_F2R2_FB16

#define	CAN_F2R2_FB17

#define	CAN_F2R2_FB18

#define	CAN_F2R2_FB19

#define	CAN_F2R2_FB20

#define	CAN_F2R2_FB21

#define	CAN_F2R2_FB22

#define	CAN_F2R2_FB23

#define	CAN_F2R2_FB24

#define	CAN_F2R2_FB25

#define	CAN_F2R2_FB26

#define	CAN_F2R2_FB27

#define	CAN_F2R2_FB28

#define	CAN_F2R2_FB29

#define	CAN_F2R2_FB30

#define	CAN_F2R2_FB31

#define	CAN_F3R2_FB0

#define	CAN_F3R2_FB1

#define	CAN_F3R2_FB2

#define	CAN_F3R2_FB3

#define	CAN_F3R2_FB4

#define	CAN_F3R2_FB5

#define	CAN_F3R2_FB6

#define	CAN_F3R2_FB7

#define	CAN_F3R2_FB8

#define	CAN_F3R2_FB9

#define	CAN_F3R2_FB10

#define	CAN_F3R2_FB11

#define	CAN_F3R2_FB12

#define	CAN_F3R2_FB13

#define	CAN_F3R2_FB14

#define	CAN_F3R2_FB15

#define	CAN_F3R2_FB16

#define	CAN_F3R2_FB17

#define	CAN_F3R2_FB18

#define	CAN_F3R2_FB19

#define	CAN_F3R2_FB20

#define	CAN_F3R2_FB21

#define	CAN_F3R2_FB22

#define	CAN_F3R2_FB23

#define	CAN_F3R2_FB24

#define	CAN_F3R2_FB25

#define	CAN_F3R2_FB26

#define	CAN_F3R2_FB27

#define	CAN_F3R2_FB28

#define	CAN_F3R2_FB29

#define	CAN_F3R2_FB30

#define	CAN_F3R2_FB31

#define	CAN_F4R2_FB0

#define	CAN_F4R2_FB1

#define	CAN_F4R2_FB2

#define	CAN_F4R2_FB3

#define	CAN_F4R2_FB4

#define	CAN_F4R2_FB5

#define	CAN_F4R2_FB6

#define	CAN_F4R2_FB7

#define	CAN_F4R2_FB8

#define	CAN_F4R2_FB9

#define	CAN_F4R2_FB10

#define	CAN_F4R2_FB11

#define	CAN_F4R2_FB12

#define	CAN_F4R2_FB13

#define	CAN_F4R2_FB14

#define	CAN_F4R2_FB15

#define	CAN_F4R2_FB16

#define	CAN_F4R2_FB17

#define	CAN_F4R2_FB18

#define	CAN_F4R2_FB19

#define	CAN_F4R2_FB20

#define	CAN_F4R2_FB21

#define	CAN_F4R2_FB22

#define	CAN_F4R2_FB23

#define	CAN_F4R2_FB24

#define	CAN_F4R2_FB25

#define	CAN_F4R2_FB26

#define	CAN_F4R2_FB27

#define	CAN_F4R2_FB28

#define	CAN_F4R2_FB29

#define	CAN_F4R2_FB30

#define	CAN_F4R2_FB31

#define	CAN_F5R2_FB0

#define	CAN_F5R2_FB1

#define	CAN_F5R2_FB2

#define	CAN_F5R2_FB3

#define	CAN_F5R2_FB4

#define	CAN_F5R2_FB5

#define	CAN_F5R2_FB6

#define	CAN_F5R2_FB7

#define	CAN_F5R2_FB8

#define	CAN_F5R2_FB9

#define	CAN_F5R2_FB10

#define	CAN_F5R2_FB11

#define	CAN_F5R2_FB12

#define	CAN_F5R2_FB13

#define	CAN_F5R2_FB14

#define	CAN_F5R2_FB15

#define	CAN_F5R2_FB16

#define	CAN_F5R2_FB17

#define	CAN_F5R2_FB18

#define	CAN_F5R2_FB19

#define	CAN_F5R2_FB20

#define	CAN_F5R2_FB21

#define	CAN_F5R2_FB22

#define	CAN_F5R2_FB23

#define	CAN_F5R2_FB24

#define	CAN_F5R2_FB25

#define	CAN_F5R2_FB26

#define	CAN_F5R2_FB27

#define	CAN_F5R2_FB28

#define	CAN_F5R2_FB29

#define	CAN_F5R2_FB30

#define	CAN_F5R2_FB31

#define	CAN_F6R2_FB0

#define	CAN_F6R2_FB1

#define	CAN_F6R2_FB2

#define	CAN_F6R2_FB3

#define	CAN_F6R2_FB4

#define	CAN_F6R2_FB5

#define	CAN_F6R2_FB6

#define	CAN_F6R2_FB7

#define	CAN_F6R2_FB8

#define	CAN_F6R2_FB9

#define	CAN_F6R2_FB10

#define	CAN_F6R2_FB11

#define	CAN_F6R2_FB12

#define	CAN_F6R2_FB13

#define	CAN_F6R2_FB14

#define	CAN_F6R2_FB15

#define	CAN_F6R2_FB16

#define	CAN_F6R2_FB17

#define	CAN_F6R2_FB18

#define	CAN_F6R2_FB19

#define	CAN_F6R2_FB20

#define	CAN_F6R2_FB21

#define	CAN_F6R2_FB22

#define	CAN_F6R2_FB23

#define	CAN_F6R2_FB24

#define	CAN_F6R2_FB25

#define	CAN_F6R2_FB26

#define	CAN_F6R2_FB27

#define	CAN_F6R2_FB28

#define	CAN_F6R2_FB29

#define	CAN_F6R2_FB30

#define	CAN_F6R2_FB31

#define	CAN_F7R2_FB0

#define	CAN_F7R2_FB1

#define	CAN_F7R2_FB2

#define	CAN_F7R2_FB3

#define	CAN_F7R2_FB4

#define	CAN_F7R2_FB5

#define	CAN_F7R2_FB6

#define	CAN_F7R2_FB7

#define	CAN_F7R2_FB8

#define	CAN_F7R2_FB9

#define	CAN_F7R2_FB10

#define	CAN_F7R2_FB11

#define	CAN_F7R2_FB12

#define	CAN_F7R2_FB13

#define	CAN_F7R2_FB14

#define	CAN_F7R2_FB15

#define	CAN_F7R2_FB16

#define	CAN_F7R2_FB17

#define	CAN_F7R2_FB18

#define	CAN_F7R2_FB19

#define	CAN_F7R2_FB20

#define	CAN_F7R2_FB21

#define	CAN_F7R2_FB22

#define	CAN_F7R2_FB23

#define	CAN_F7R2_FB24

#define	CAN_F7R2_FB25

#define	CAN_F7R2_FB26

#define	CAN_F7R2_FB27

#define	CAN_F7R2_FB28

#define	CAN_F7R2_FB29

#define	CAN_F7R2_FB30

#define	CAN_F7R2_FB31

#define	CAN_F8R2_FB0

#define	CAN_F8R2_FB1

#define	CAN_F8R2_FB2

#define	CAN_F8R2_FB3

#define	CAN_F8R2_FB4

#define	CAN_F8R2_FB5

#define	CAN_F8R2_FB6

#define	CAN_F8R2_FB7

#define	CAN_F8R2_FB8

#define	CAN_F8R2_FB9

#define	CAN_F8R2_FB10

#define	CAN_F8R2_FB11

#define	CAN_F8R2_FB12

#define	CAN_F8R2_FB13

#define	CAN_F8R2_FB14

#define	CAN_F8R2_FB15

#define	CAN_F8R2_FB16

#define	CAN_F8R2_FB17

#define	CAN_F8R2_FB18

#define	CAN_F8R2_FB19

#define	CAN_F8R2_FB20

#define	CAN_F8R2_FB21

#define	CAN_F8R2_FB22

#define	CAN_F8R2_FB23

#define	CAN_F8R2_FB24

#define	CAN_F8R2_FB25

#define	CAN_F8R2_FB26

#define	CAN_F8R2_FB27

#define	CAN_F8R2_FB28

#define	CAN_F8R2_FB29

#define	CAN_F8R2_FB30

#define	CAN_F8R2_FB31

#define	CAN_F9R2_FB0

#define	CAN_F9R2_FB1

#define	CAN_F9R2_FB2

#define	CAN_F9R2_FB3

#define	CAN_F9R2_FB4

#define	CAN_F9R2_FB5

#define	CAN_F9R2_FB6

#define	CAN_F9R2_FB7

#define	CAN_F9R2_FB8

#define	CAN_F9R2_FB9

#define	CAN_F9R2_FB10

#define	CAN_F9R2_FB11

#define	CAN_F9R2_FB12

#define	CAN_F9R2_FB13

#define	CAN_F9R2_FB14

#define	CAN_F9R2_FB15

#define	CAN_F9R2_FB16

#define	CAN_F9R2_FB17

#define	CAN_F9R2_FB18

#define	CAN_F9R2_FB19

#define	CAN_F9R2_FB20

#define	CAN_F9R2_FB21

#define	CAN_F9R2_FB22

#define	CAN_F9R2_FB23

#define	CAN_F9R2_FB24

#define	CAN_F9R2_FB25

#define	CAN_F9R2_FB26

#define	CAN_F9R2_FB27

#define	CAN_F9R2_FB28

#define	CAN_F9R2_FB29

#define	CAN_F9R2_FB30

#define	CAN_F9R2_FB31

#define	CAN_F10R2_FB0

#define	CAN_F10R2_FB1

#define	CAN_F10R2_FB2

#define	CAN_F10R2_FB3

#define	CAN_F10R2_FB4

#define	CAN_F10R2_FB5

#define	CAN_F10R2_FB6

#define	CAN_F10R2_FB7

#define	CAN_F10R2_FB8

#define	CAN_F10R2_FB9

#define	CAN_F10R2_FB10

#define	CAN_F10R2_FB11

#define	CAN_F10R2_FB12

#define	CAN_F10R2_FB13

#define	CAN_F10R2_FB14

#define	CAN_F10R2_FB15

#define	CAN_F10R2_FB16

#define	CAN_F10R2_FB17

#define	CAN_F10R2_FB18

#define	CAN_F10R2_FB19

#define	CAN_F10R2_FB20

#define	CAN_F10R2_FB21

#define	CAN_F10R2_FB22

#define	CAN_F10R2_FB23

#define	CAN_F10R2_FB24

#define	CAN_F10R2_FB25

#define	CAN_F10R2_FB26

#define	CAN_F10R2_FB27

#define	CAN_F10R2_FB28

#define	CAN_F10R2_FB29

#define	CAN_F10R2_FB30

#define	CAN_F10R2_FB31

#define	CAN_F11R2_FB0

#define	CAN_F11R2_FB1

#define	CAN_F11R2_FB2

#define	CAN_F11R2_FB3

#define	CAN_F11R2_FB4

#define	CAN_F11R2_FB5

#define	CAN_F11R2_FB6

#define	CAN_F11R2_FB7

#define	CAN_F11R2_FB8

#define	CAN_F11R2_FB9

#define	CAN_F11R2_FB10

#define	CAN_F11R2_FB11

#define	CAN_F11R2_FB12

#define	CAN_F11R2_FB13

#define	CAN_F11R2_FB14

#define	CAN_F11R2_FB15

#define	CAN_F11R2_FB16

#define	CAN_F11R2_FB17

#define	CAN_F11R2_FB18

#define	CAN_F11R2_FB19

#define	CAN_F11R2_FB20

#define	CAN_F11R2_FB21

#define	CAN_F11R2_FB22

#define	CAN_F11R2_FB23

#define	CAN_F11R2_FB24

#define	CAN_F11R2_FB25

#define	CAN_F11R2_FB26

#define	CAN_F11R2_FB27

#define	CAN_F11R2_FB28

#define	CAN_F11R2_FB29

#define	CAN_F11R2_FB30

#define	CAN_F11R2_FB31

#define	CAN_F12R2_FB0

#define	CAN_F12R2_FB1

#define	CAN_F12R2_FB2

#define	CAN_F12R2_FB3

#define	CAN_F12R2_FB4

#define	CAN_F12R2_FB5

#define	CAN_F12R2_FB6

#define	CAN_F12R2_FB7

#define	CAN_F12R2_FB8

#define	CAN_F12R2_FB9

#define	CAN_F12R2_FB10

#define	CAN_F12R2_FB11

#define	CAN_F12R2_FB12

#define	CAN_F12R2_FB13

#define	CAN_F12R2_FB14

#define	CAN_F12R2_FB15

#define	CAN_F12R2_FB16

#define	CAN_F12R2_FB17

#define	CAN_F12R2_FB18

#define	CAN_F12R2_FB19

#define	CAN_F12R2_FB20

#define	CAN_F12R2_FB21

#define	CAN_F12R2_FB22

#define	CAN_F12R2_FB23

#define	CAN_F12R2_FB24

#define	CAN_F12R2_FB25

#define	CAN_F12R2_FB26

#define	CAN_F12R2_FB27

#define	CAN_F12R2_FB28

#define	CAN_F12R2_FB29

#define	CAN_F12R2_FB30

#define	CAN_F12R2_FB31

#define	CAN_F13R2_FB0

#define	CAN_F13R2_FB1

#define	CAN_F13R2_FB2

#define	CAN_F13R2_FB3

#define	CAN_F13R2_FB4

#define	CAN_F13R2_FB5

#define	CAN_F13R2_FB6

#define	CAN_F13R2_FB7

#define	CAN_F13R2_FB8

#define	CAN_F13R2_FB9

#define	CAN_F13R2_FB10

#define	CAN_F13R2_FB11

#define	CAN_F13R2_FB12

#define	CAN_F13R2_FB13

#define	CAN_F13R2_FB14

#define	CAN_F13R2_FB15

#define	CAN_F13R2_FB16

#define	CAN_F13R2_FB17

#define	CAN_F13R2_FB18

#define	CAN_F13R2_FB19

#define	CAN_F13R2_FB20

#define	CAN_F13R2_FB21

#define	CAN_F13R2_FB22

#define	CAN_F13R2_FB23

#define	CAN_F13R2_FB24

#define	CAN_F13R2_FB25

#define	CAN_F13R2_FB26

#define	CAN_F13R2_FB27

#define	CAN_F13R2_FB28

#define	CAN_F13R2_FB29

#define	CAN_F13R2_FB30

#define	CAN_F13R2_FB31

#define	CRC_DR_DR

#define	CRC_IDR_IDR

#define	CRC_CR_RESET

#define	DAC_CR_EN1

#define	DAC_CR_BOFF1

#define	DAC_CR_TEN1

#define	DAC_CR_TSEL1

#define	DAC_CR_TSEL1_0

#define	DAC_CR_TSEL1_1

#define	DAC_CR_TSEL1_2

#define	DAC_CR_WAVE1

#define	DAC_CR_WAVE1_0

#define	DAC_CR_WAVE1_1

#define	DAC_CR_MAMP1

#define	DAC_CR_MAMP1_0

#define	DAC_CR_MAMP1_1

#define	DAC_CR_MAMP1_2

#define	DAC_CR_MAMP1_3

#define	DAC_CR_DMAEN1

#define	DAC_CR_EN2

#define	DAC_CR_BOFF2

#define	DAC_CR_TEN2

#define	DAC_CR_TSEL2

#define	DAC_CR_TSEL2_0

#define	DAC_CR_TSEL2_1

#define	DAC_CR_TSEL2_2

#define	DAC_CR_WAVE2

#define	DAC_CR_WAVE2_0

#define	DAC_CR_WAVE2_1

#define	DAC_CR_MAMP2

#define	DAC_CR_MAMP2_0

#define	DAC_CR_MAMP2_1

#define	DAC_CR_MAMP2_2

#define	DAC_CR_MAMP2_3

#define	DAC_CR_DMAEN2

#define	DAC_SWTRIGR_SWTRIG1

#define	DAC_SWTRIGR_SWTRIG2

#define	DAC_DHR12R1_DACC1DHR

#define	DAC_DHR12L1_DACC1DHR

#define	DAC_DHR8R1_DACC1DHR

#define	DAC_DHR12R2_DACC2DHR

#define	DAC_DHR12L2_DACC2DHR

#define	DAC_DHR8R2_DACC2DHR

#define	DAC_DHR12RD_DACC1DHR

#define	DAC_DHR12RD_DACC2DHR

#define	DAC_DHR12LD_DACC1DHR

#define	DAC_DHR12LD_DACC2DHR

#define	DAC_DHR8RD_DACC1DHR

#define	DAC_DHR8RD_DACC2DHR

#define	DAC_DOR1_DACC1DOR

#define	DAC_DOR2_DACC2DOR

#define	DAC_SR_DMAUDR1

#define	DAC_SR_DMAUDR2

#define	EXTI_IMR_MR0

#define	EXTI_IMR_MR1

#define	EXTI_IMR_MR2

#define	EXTI_IMR_MR3

#define	EXTI_IMR_MR4

#define	EXTI_IMR_MR5

#define	EXTI_IMR_MR6

#define	EXTI_IMR_MR7

#define	EXTI_IMR_MR8

#define	EXTI_IMR_MR9

#define	EXTI_IMR_MR10

#define	EXTI_IMR_MR11

#define	EXTI_IMR_MR12

#define	EXTI_IMR_MR13

#define	EXTI_IMR_MR14

#define	EXTI_IMR_MR15

#define	EXTI_IMR_MR16

#define	EXTI_IMR_MR17

#define	EXTI_IMR_MR18

#define	EXTI_IMR_MR19

#define	EXTI_EMR_MR0

#define	EXTI_EMR_MR1

#define	EXTI_EMR_MR2

#define	EXTI_EMR_MR3

#define	EXTI_EMR_MR4

#define	EXTI_EMR_MR5

#define	EXTI_EMR_MR6

#define	EXTI_EMR_MR7

#define	EXTI_EMR_MR8

#define	EXTI_EMR_MR9

#define	EXTI_EMR_MR10

#define	EXTI_EMR_MR11

#define	EXTI_EMR_MR12

#define	EXTI_EMR_MR13

#define	EXTI_EMR_MR14

#define	EXTI_EMR_MR15

#define	EXTI_EMR_MR16

#define	EXTI_EMR_MR17

#define	EXTI_EMR_MR18

#define	EXTI_EMR_MR19

#define	EXTI_RTSR_TR0

#define	EXTI_RTSR_TR1

#define	EXTI_RTSR_TR2

#define	EXTI_RTSR_TR3

#define	EXTI_RTSR_TR4

#define	EXTI_RTSR_TR5

#define	EXTI_RTSR_TR6

#define	EXTI_RTSR_TR7

#define	EXTI_RTSR_TR8

#define	EXTI_RTSR_TR9

#define	EXTI_RTSR_TR10

#define	EXTI_RTSR_TR11

#define	EXTI_RTSR_TR12

#define	EXTI_RTSR_TR13

#define	EXTI_RTSR_TR14

#define	EXTI_RTSR_TR15

#define	EXTI_RTSR_TR16

#define	EXTI_RTSR_TR17

#define	EXTI_RTSR_TR18

#define	EXTI_RTSR_TR19

#define	EXTI_FTSR_TR0

#define	EXTI_FTSR_TR1

#define	EXTI_FTSR_TR2

#define	EXTI_FTSR_TR3

#define	EXTI_FTSR_TR4

#define	EXTI_FTSR_TR5

#define	EXTI_FTSR_TR6

#define	EXTI_FTSR_TR7

#define	EXTI_FTSR_TR8

#define	EXTI_FTSR_TR9

#define	EXTI_FTSR_TR10

#define	EXTI_FTSR_TR11

#define	EXTI_FTSR_TR12

#define	EXTI_FTSR_TR13

#define	EXTI_FTSR_TR14

#define	EXTI_FTSR_TR15

#define	EXTI_FTSR_TR16

#define	EXTI_FTSR_TR17

#define	EXTI_FTSR_TR18

#define	EXTI_FTSR_TR19

#define	EXTI_SWIER_SWIER0

#define	EXTI_SWIER_SWIER1

#define	EXTI_SWIER_SWIER2

#define	EXTI_SWIER_SWIER3

#define	EXTI_SWIER_SWIER4

#define	EXTI_SWIER_SWIER5

#define	EXTI_SWIER_SWIER6

#define	EXTI_SWIER_SWIER7

#define	EXTI_SWIER_SWIER8

#define	EXTI_SWIER_SWIER9

#define	EXTI_SWIER_SWIER10

#define	EXTI_SWIER_SWIER11

#define	EXTI_SWIER_SWIER12

#define	EXTI_SWIER_SWIER13

#define	EXTI_SWIER_SWIER14

#define	EXTI_SWIER_SWIER15

#define	EXTI_SWIER_SWIER16

#define	EXTI_SWIER_SWIER17

#define	EXTI_SWIER_SWIER18

#define	EXTI_SWIER_SWIER19

#define	EXTI_PR_PR0

#define	EXTI_PR_PR1

#define	EXTI_PR_PR2

#define	EXTI_PR_PR3

#define	EXTI_PR_PR4

#define	EXTI_PR_PR5

#define	EXTI_PR_PR6

#define	EXTI_PR_PR7

#define	EXTI_PR_PR8

#define	EXTI_PR_PR9

#define	EXTI_PR_PR10

#define	EXTI_PR_PR11

#define	EXTI_PR_PR12

#define	EXTI_PR_PR13

#define	EXTI_PR_PR14

#define	EXTI_PR_PR15

#define	EXTI_PR_PR16

#define	EXTI_PR_PR17

#define	EXTI_PR_PR18

#define	EXTI_PR_PR19

#define	FSMC_BCR1_MBKEN

#define	FSMC_BCR1_MUXEN

#define	FSMC_BCR1_MTYP

#define	FSMC_BCR1_MTYP_0

#define	FSMC_BCR1_MTYP_1

#define	FSMC_BCR1_MWID

#define	FSMC_BCR1_MWID_0

#define	FSMC_BCR1_MWID_1

#define	FSMC_BCR1_FACCEN

#define	FSMC_BCR1_BURSTEN

#define	FSMC_BCR1_WAITPOL

#define	FSMC_BCR1_WRAPMOD

#define	FSMC_BCR1_WAITCFG

#define	FSMC_BCR1_WREN

#define	FSMC_BCR1_WAITEN

#define	FSMC_BCR1_EXTMOD

#define	FSMC_BCR1_ASYNCWAIT

#define	FSMC_BCR1_CBURSTRW

#define	FSMC_BCR2_MBKEN

#define	FSMC_BCR2_MUXEN

#define	FSMC_BCR2_MTYP

#define	FSMC_BCR2_MTYP_0

#define	FSMC_BCR2_MTYP_1

#define	FSMC_BCR2_MWID

#define	FSMC_BCR2_MWID_0

#define	FSMC_BCR2_MWID_1

#define	FSMC_BCR2_FACCEN

#define	FSMC_BCR2_BURSTEN

#define	FSMC_BCR2_WAITPOL

#define	FSMC_BCR2_WRAPMOD

#define	FSMC_BCR2_WAITCFG

#define	FSMC_BCR2_WREN

#define	FSMC_BCR2_WAITEN

#define	FSMC_BCR2_EXTMOD

#define	FSMC_BCR2_ASYNCWAIT

#define	FSMC_BCR2_CBURSTRW

#define	FSMC_BCR3_MBKEN

#define	FSMC_BCR3_MUXEN

#define	FSMC_BCR3_MTYP

#define	FSMC_BCR3_MTYP_0

#define	FSMC_BCR3_MTYP_1

#define	FSMC_BCR3_MWID

#define	FSMC_BCR3_MWID_0

#define	FSMC_BCR3_MWID_1

#define	FSMC_BCR3_FACCEN

#define	FSMC_BCR3_BURSTEN

#define	FSMC_BCR3_WAITPOL

#define	FSMC_BCR3_WRAPMOD

#define	FSMC_BCR3_WAITCFG

#define	FSMC_BCR3_WREN

#define	FSMC_BCR3_WAITEN

#define	FSMC_BCR3_EXTMOD

#define	FSMC_BCR3_ASYNCWAIT

#define	FSMC_BCR3_CBURSTRW

#define	FSMC_BCR4_MBKEN

#define	FSMC_BCR4_MUXEN

#define	FSMC_BCR4_MTYP

#define	FSMC_BCR4_MTYP_0

#define	FSMC_BCR4_MTYP_1

#define	FSMC_BCR4_MWID

#define	FSMC_BCR4_MWID_0

#define	FSMC_BCR4_MWID_1

#define	FSMC_BCR4_FACCEN

#define	FSMC_BCR4_BURSTEN

#define	FSMC_BCR4_WAITPOL

#define	FSMC_BCR4_WRAPMOD

#define	FSMC_BCR4_WAITCFG

#define	FSMC_BCR4_WREN

#define	FSMC_BCR4_WAITEN

#define	FSMC_BCR4_EXTMOD

#define	FSMC_BCR4_ASYNCWAIT

#define	FSMC_BCR4_CBURSTRW

#define	FSMC_BTR1_ADDSET

#define	FSMC_BTR1_ADDSET_0

#define	FSMC_BTR1_ADDSET_1

#define	FSMC_BTR1_ADDSET_2

#define	FSMC_BTR1_ADDSET_3

#define	FSMC_BTR1_ADDHLD

#define	FSMC_BTR1_ADDHLD_0

#define	FSMC_BTR1_ADDHLD_1

#define	FSMC_BTR1_ADDHLD_2

#define	FSMC_BTR1_ADDHLD_3

#define	FSMC_BTR1_DATAST

#define	FSMC_BTR1_DATAST_0

#define	FSMC_BTR1_DATAST_1

#define	FSMC_BTR1_DATAST_2

#define	FSMC_BTR1_DATAST_3

#define	FSMC_BTR1_BUSTURN

#define	FSMC_BTR1_BUSTURN_0

#define	FSMC_BTR1_BUSTURN_1

#define	FSMC_BTR1_BUSTURN_2

#define	FSMC_BTR1_BUSTURN_3

#define	FSMC_BTR1_CLKDIV

#define	FSMC_BTR1_CLKDIV_0

#define	FSMC_BTR1_CLKDIV_1

#define	FSMC_BTR1_CLKDIV_2

#define	FSMC_BTR1_CLKDIV_3

#define	FSMC_BTR1_DATLAT

#define	FSMC_BTR1_DATLAT_0

#define	FSMC_BTR1_DATLAT_1

#define	FSMC_BTR1_DATLAT_2

#define	FSMC_BTR1_DATLAT_3

#define	FSMC_BTR1_ACCMOD

#define	FSMC_BTR1_ACCMOD_0

#define	FSMC_BTR1_ACCMOD_1

#define	FSMC_BTR2_ADDSET

#define	FSMC_BTR2_ADDSET_0

#define	FSMC_BTR2_ADDSET_1

#define	FSMC_BTR2_ADDSET_2

#define	FSMC_BTR2_ADDSET_3

#define	FSMC_BTR2_ADDHLD

#define	FSMC_BTR2_ADDHLD_0

#define	FSMC_BTR2_ADDHLD_1

#define	FSMC_BTR2_ADDHLD_2

#define	FSMC_BTR2_ADDHLD_3

#define	FSMC_BTR2_DATAST

#define	FSMC_BTR2_DATAST_0

#define	FSMC_BTR2_DATAST_1

#define	FSMC_BTR2_DATAST_2

#define	FSMC_BTR2_DATAST_3

#define	FSMC_BTR2_BUSTURN

#define	FSMC_BTR2_BUSTURN_0

#define	FSMC_BTR2_BUSTURN_1

#define	FSMC_BTR2_BUSTURN_2

#define	FSMC_BTR2_BUSTURN_3

#define	FSMC_BTR2_CLKDIV

#define	FSMC_BTR2_CLKDIV_0

#define	FSMC_BTR2_CLKDIV_1

#define	FSMC_BTR2_CLKDIV_2

#define	FSMC_BTR2_CLKDIV_3

#define	FSMC_BTR2_DATLAT

#define	FSMC_BTR2_DATLAT_0

#define	FSMC_BTR2_DATLAT_1

#define	FSMC_BTR2_DATLAT_2

#define	FSMC_BTR2_DATLAT_3

#define	FSMC_BTR2_ACCMOD

#define	FSMC_BTR2_ACCMOD_0

#define	FSMC_BTR2_ACCMOD_1

#define	FSMC_BTR3_ADDSET

#define	FSMC_BTR3_ADDSET_0

#define	FSMC_BTR3_ADDSET_1

#define	FSMC_BTR3_ADDSET_2

#define	FSMC_BTR3_ADDSET_3

#define	FSMC_BTR3_ADDHLD

#define	FSMC_BTR3_ADDHLD_0

#define	FSMC_BTR3_ADDHLD_1

#define	FSMC_BTR3_ADDHLD_2

#define	FSMC_BTR3_ADDHLD_3

#define	FSMC_BTR3_DATAST

#define	FSMC_BTR3_DATAST_0

#define	FSMC_BTR3_DATAST_1

#define	FSMC_BTR3_DATAST_2

#define	FSMC_BTR3_DATAST_3

#define	FSMC_BTR3_BUSTURN

#define	FSMC_BTR3_BUSTURN_0

#define	FSMC_BTR3_BUSTURN_1

#define	FSMC_BTR3_BUSTURN_2

#define	FSMC_BTR3_BUSTURN_3

#define	FSMC_BTR3_CLKDIV

#define	FSMC_BTR3_CLKDIV_0

#define	FSMC_BTR3_CLKDIV_1

#define	FSMC_BTR3_CLKDIV_2

#define	FSMC_BTR3_CLKDIV_3

#define	FSMC_BTR3_DATLAT

#define	FSMC_BTR3_DATLAT_0

#define	FSMC_BTR3_DATLAT_1

#define	FSMC_BTR3_DATLAT_2

#define	FSMC_BTR3_DATLAT_3

#define	FSMC_BTR3_ACCMOD

#define	FSMC_BTR3_ACCMOD_0

#define	FSMC_BTR3_ACCMOD_1

#define	FSMC_BTR4_ADDSET

#define	FSMC_BTR4_ADDSET_0

#define	FSMC_BTR4_ADDSET_1

#define	FSMC_BTR4_ADDSET_2

#define	FSMC_BTR4_ADDSET_3

#define	FSMC_BTR4_ADDHLD

#define	FSMC_BTR4_ADDHLD_0

#define	FSMC_BTR4_ADDHLD_1

#define	FSMC_BTR4_ADDHLD_2

#define	FSMC_BTR4_ADDHLD_3

#define	FSMC_BTR4_DATAST

#define	FSMC_BTR4_DATAST_0

#define	FSMC_BTR4_DATAST_1

#define	FSMC_BTR4_DATAST_2

#define	FSMC_BTR4_DATAST_3

#define	FSMC_BTR4_BUSTURN

#define	FSMC_BTR4_BUSTURN_0

#define	FSMC_BTR4_BUSTURN_1

#define	FSMC_BTR4_BUSTURN_2

#define	FSMC_BTR4_BUSTURN_3

#define	FSMC_BTR4_CLKDIV

#define	FSMC_BTR4_CLKDIV_0

#define	FSMC_BTR4_CLKDIV_1

#define	FSMC_BTR4_CLKDIV_2

#define	FSMC_BTR4_CLKDIV_3

#define	FSMC_BTR4_DATLAT

#define	FSMC_BTR4_DATLAT_0

#define	FSMC_BTR4_DATLAT_1

#define	FSMC_BTR4_DATLAT_2

#define	FSMC_BTR4_DATLAT_3

#define	FSMC_BTR4_ACCMOD

#define	FSMC_BTR4_ACCMOD_0

#define	FSMC_BTR4_ACCMOD_1

#define	FSMC_BWTR1_ADDSET

#define	FSMC_BWTR1_ADDSET_0

#define	FSMC_BWTR1_ADDSET_1

#define	FSMC_BWTR1_ADDSET_2

#define	FSMC_BWTR1_ADDSET_3

#define	FSMC_BWTR1_ADDHLD

#define	FSMC_BWTR1_ADDHLD_0

#define	FSMC_BWTR1_ADDHLD_1

#define	FSMC_BWTR1_ADDHLD_2

#define	FSMC_BWTR1_ADDHLD_3

#define	FSMC_BWTR1_DATAST

#define	FSMC_BWTR1_DATAST_0

#define	FSMC_BWTR1_DATAST_1

#define	FSMC_BWTR1_DATAST_2

#define	FSMC_BWTR1_DATAST_3

#define	FSMC_BWTR1_CLKDIV

#define	FSMC_BWTR1_CLKDIV_0

#define	FSMC_BWTR1_CLKDIV_1

#define	FSMC_BWTR1_CLKDIV_2

#define	FSMC_BWTR1_CLKDIV_3

#define	FSMC_BWTR1_DATLAT

#define	FSMC_BWTR1_DATLAT_0

#define	FSMC_BWTR1_DATLAT_1

#define	FSMC_BWTR1_DATLAT_2

#define	FSMC_BWTR1_DATLAT_3

#define	FSMC_BWTR1_ACCMOD

#define	FSMC_BWTR1_ACCMOD_0

#define	FSMC_BWTR1_ACCMOD_1

#define	FSMC_BWTR2_ADDSET

#define	FSMC_BWTR2_ADDSET_0

#define	FSMC_BWTR2_ADDSET_1

#define	FSMC_BWTR2_ADDSET_2

#define	FSMC_BWTR2_ADDSET_3

#define	FSMC_BWTR2_ADDHLD

#define	FSMC_BWTR2_ADDHLD_0

#define	FSMC_BWTR2_ADDHLD_1

#define	FSMC_BWTR2_ADDHLD_2

#define	FSMC_BWTR2_ADDHLD_3

#define	FSMC_BWTR2_DATAST

#define	FSMC_BWTR2_DATAST_0

#define	FSMC_BWTR2_DATAST_1

#define	FSMC_BWTR2_DATAST_2

#define	FSMC_BWTR2_DATAST_3

#define	FSMC_BWTR2_CLKDIV

#define	FSMC_BWTR2_CLKDIV_0

#define	FSMC_BWTR2_CLKDIV_1

#define	FSMC_BWTR2_CLKDIV_2

#define	FSMC_BWTR2_CLKDIV_3

#define	FSMC_BWTR2_DATLAT

#define	FSMC_BWTR2_DATLAT_0

#define	FSMC_BWTR2_DATLAT_1

#define	FSMC_BWTR2_DATLAT_2

#define	FSMC_BWTR2_DATLAT_3

#define	FSMC_BWTR2_ACCMOD

#define	FSMC_BWTR2_ACCMOD_0

#define	FSMC_BWTR2_ACCMOD_1

#define	FSMC_BWTR3_ADDSET

#define	FSMC_BWTR3_ADDSET_0

#define	FSMC_BWTR3_ADDSET_1

#define	FSMC_BWTR3_ADDSET_2

#define	FSMC_BWTR3_ADDSET_3

#define	FSMC_BWTR3_ADDHLD

#define	FSMC_BWTR3_ADDHLD_0

#define	FSMC_BWTR3_ADDHLD_1

#define	FSMC_BWTR3_ADDHLD_2

#define	FSMC_BWTR3_ADDHLD_3

#define	FSMC_BWTR3_DATAST

#define	FSMC_BWTR3_DATAST_0

#define	FSMC_BWTR3_DATAST_1

#define	FSMC_BWTR3_DATAST_2

#define	FSMC_BWTR3_DATAST_3

#define	FSMC_BWTR3_CLKDIV

#define	FSMC_BWTR3_CLKDIV_0

#define	FSMC_BWTR3_CLKDIV_1

#define	FSMC_BWTR3_CLKDIV_2

#define	FSMC_BWTR3_CLKDIV_3

#define	FSMC_BWTR3_DATLAT

#define	FSMC_BWTR3_DATLAT_0

#define	FSMC_BWTR3_DATLAT_1

#define	FSMC_BWTR3_DATLAT_2

#define	FSMC_BWTR3_DATLAT_3

#define	FSMC_BWTR3_ACCMOD

#define	FSMC_BWTR3_ACCMOD_0

#define	FSMC_BWTR3_ACCMOD_1

#define	FSMC_BWTR4_ADDSET

#define	FSMC_BWTR4_ADDSET_0

#define	FSMC_BWTR4_ADDSET_1

#define	FSMC_BWTR4_ADDSET_2

#define	FSMC_BWTR4_ADDSET_3

#define	FSMC_BWTR4_ADDHLD

#define	FSMC_BWTR4_ADDHLD_0

#define	FSMC_BWTR4_ADDHLD_1

#define	FSMC_BWTR4_ADDHLD_2

#define	FSMC_BWTR4_ADDHLD_3

#define	FSMC_BWTR4_DATAST

#define	FSMC_BWTR4_DATAST_0

#define	FSMC_BWTR4_DATAST_1

#define	FSMC_BWTR4_DATAST_2

#define	FSMC_BWTR4_DATAST_3

#define	FSMC_BWTR4_CLKDIV

#define	FSMC_BWTR4_CLKDIV_0

#define	FSMC_BWTR4_CLKDIV_1

#define	FSMC_BWTR4_CLKDIV_2

#define	FSMC_BWTR4_CLKDIV_3

#define	FSMC_BWTR4_DATLAT

#define	FSMC_BWTR4_DATLAT_0

#define	FSMC_BWTR4_DATLAT_1

#define	FSMC_BWTR4_DATLAT_2

#define	FSMC_BWTR4_DATLAT_3

#define	FSMC_BWTR4_ACCMOD

#define	FSMC_BWTR4_ACCMOD_0

#define	FSMC_BWTR4_ACCMOD_1

#define	FSMC_PCR2_PWAITEN

#define	FSMC_PCR2_PBKEN

#define	FSMC_PCR2_PTYP

#define	FSMC_PCR2_PWID

#define	FSMC_PCR2_PWID_0

#define	FSMC_PCR2_PWID_1

#define	FSMC_PCR2_ECCEN

#define	FSMC_PCR2_TCLR

#define	FSMC_PCR2_TCLR_0

#define	FSMC_PCR2_TCLR_1

#define	FSMC_PCR2_TCLR_2

#define	FSMC_PCR2_TCLR_3

#define	FSMC_PCR2_TAR

#define	FSMC_PCR2_TAR_0

#define	FSMC_PCR2_TAR_1

#define	FSMC_PCR2_TAR_2

#define	FSMC_PCR2_TAR_3

#define	FSMC_PCR2_ECCPS

#define	FSMC_PCR2_ECCPS_0

#define	FSMC_PCR2_ECCPS_1

#define	FSMC_PCR2_ECCPS_2

#define	FSMC_PCR3_PWAITEN

#define	FSMC_PCR3_PBKEN

#define	FSMC_PCR3_PTYP

#define	FSMC_PCR3_PWID

#define	FSMC_PCR3_PWID_0

#define	FSMC_PCR3_PWID_1

#define	FSMC_PCR3_ECCEN

#define	FSMC_PCR3_TCLR

#define	FSMC_PCR3_TCLR_0

#define	FSMC_PCR3_TCLR_1

#define	FSMC_PCR3_TCLR_2

#define	FSMC_PCR3_TCLR_3

#define	FSMC_PCR3_TAR

#define	FSMC_PCR3_TAR_0

#define	FSMC_PCR3_TAR_1

#define	FSMC_PCR3_TAR_2

#define	FSMC_PCR3_TAR_3

#define	FSMC_PCR3_ECCPS

#define	FSMC_PCR3_ECCPS_0

#define	FSMC_PCR3_ECCPS_1

#define	FSMC_PCR3_ECCPS_2

#define	FSMC_PCR4_PWAITEN

#define	FSMC_PCR4_PBKEN

#define	FSMC_PCR4_PTYP

#define	FSMC_PCR4_PWID

#define	FSMC_PCR4_PWID_0

#define	FSMC_PCR4_PWID_1

#define	FSMC_PCR4_ECCEN

#define	FSMC_PCR4_TCLR

#define	FSMC_PCR4_TCLR_0

#define	FSMC_PCR4_TCLR_1

#define	FSMC_PCR4_TCLR_2

#define	FSMC_PCR4_TCLR_3

#define	FSMC_PCR4_TAR

#define	FSMC_PCR4_TAR_0

#define	FSMC_PCR4_TAR_1

#define	FSMC_PCR4_TAR_2

#define	FSMC_PCR4_TAR_3

#define	FSMC_PCR4_ECCPS

#define	FSMC_PCR4_ECCPS_0

#define	FSMC_PCR4_ECCPS_1

#define	FSMC_PCR4_ECCPS_2

#define	FSMC_SR2_IRS

#define	FSMC_SR2_ILS

#define	FSMC_SR2_IFS

#define	FSMC_SR2_IREN

#define	FSMC_SR2_ILEN

#define	FSMC_SR2_IFEN

#define	FSMC_SR2_FEMPT

#define	FSMC_SR3_IRS

#define	FSMC_SR3_ILS

#define	FSMC_SR3_IFS

#define	FSMC_SR3_IREN

#define	FSMC_SR3_ILEN

#define	FSMC_SR3_IFEN

#define	FSMC_SR3_FEMPT

#define	FSMC_SR4_IRS

#define	FSMC_SR4_ILS

#define	FSMC_SR4_IFS

#define	FSMC_SR4_IREN

#define	FSMC_SR4_ILEN

#define	FSMC_SR4_IFEN

#define	FSMC_SR4_FEMPT

#define	FSMC_PMEM2_MEMSET2

#define	FSMC_PMEM2_MEMSET2_0

#define	FSMC_PMEM2_MEMSET2_1

#define	FSMC_PMEM2_MEMSET2_2

#define	FSMC_PMEM2_MEMSET2_3

#define	FSMC_PMEM2_MEMSET2_4

#define	FSMC_PMEM2_MEMSET2_5

#define	FSMC_PMEM2_MEMSET2_6

#define	FSMC_PMEM2_MEMSET2_7

#define	FSMC_PMEM2_MEMWAIT2

#define	FSMC_PMEM2_MEMWAIT2_0

#define	FSMC_PMEM2_MEMWAIT2_1

#define	FSMC_PMEM2_MEMWAIT2_2

#define	FSMC_PMEM2_MEMWAIT2_3

#define	FSMC_PMEM2_MEMWAIT2_4

#define	FSMC_PMEM2_MEMWAIT2_5

#define	FSMC_PMEM2_MEMWAIT2_6

#define	FSMC_PMEM2_MEMWAIT2_7

#define	FSMC_PMEM2_MEMHOLD2

#define	FSMC_PMEM2_MEMHOLD2_0

#define	FSMC_PMEM2_MEMHOLD2_1

#define	FSMC_PMEM2_MEMHOLD2_2

#define	FSMC_PMEM2_MEMHOLD2_3

#define	FSMC_PMEM2_MEMHOLD2_4

#define	FSMC_PMEM2_MEMHOLD2_5

#define	FSMC_PMEM2_MEMHOLD2_6

#define	FSMC_PMEM2_MEMHOLD2_7

#define	FSMC_PMEM2_MEMHIZ2

#define	FSMC_PMEM2_MEMHIZ2_0

#define	FSMC_PMEM2_MEMHIZ2_1

#define	FSMC_PMEM2_MEMHIZ2_2

#define	FSMC_PMEM2_MEMHIZ2_3

#define	FSMC_PMEM2_MEMHIZ2_4

#define	FSMC_PMEM2_MEMHIZ2_5

#define	FSMC_PMEM2_MEMHIZ2_6

#define	FSMC_PMEM2_MEMHIZ2_7

#define	FSMC_PMEM3_MEMSET3

#define	FSMC_PMEM3_MEMSET3_0

#define	FSMC_PMEM3_MEMSET3_1

#define	FSMC_PMEM3_MEMSET3_2

#define	FSMC_PMEM3_MEMSET3_3

#define	FSMC_PMEM3_MEMSET3_4

#define	FSMC_PMEM3_MEMSET3_5

#define	FSMC_PMEM3_MEMSET3_6

#define	FSMC_PMEM3_MEMSET3_7

#define	FSMC_PMEM3_MEMWAIT3

#define	FSMC_PMEM3_MEMWAIT3_0

#define	FSMC_PMEM3_MEMWAIT3_1

#define	FSMC_PMEM3_MEMWAIT3_2

#define	FSMC_PMEM3_MEMWAIT3_3

#define	FSMC_PMEM3_MEMWAIT3_4

#define	FSMC_PMEM3_MEMWAIT3_5

#define	FSMC_PMEM3_MEMWAIT3_6

#define	FSMC_PMEM3_MEMWAIT3_7

#define	FSMC_PMEM3_MEMHOLD3

#define	FSMC_PMEM3_MEMHOLD3_0

#define	FSMC_PMEM3_MEMHOLD3_1

#define	FSMC_PMEM3_MEMHOLD3_2

#define	FSMC_PMEM3_MEMHOLD3_3

#define	FSMC_PMEM3_MEMHOLD3_4

#define	FSMC_PMEM3_MEMHOLD3_5

#define	FSMC_PMEM3_MEMHOLD3_6

#define	FSMC_PMEM3_MEMHOLD3_7

#define	FSMC_PMEM3_MEMHIZ3

#define	FSMC_PMEM3_MEMHIZ3_0

#define	FSMC_PMEM3_MEMHIZ3_1

#define	FSMC_PMEM3_MEMHIZ3_2

#define	FSMC_PMEM3_MEMHIZ3_3

#define	FSMC_PMEM3_MEMHIZ3_4

#define	FSMC_PMEM3_MEMHIZ3_5

#define	FSMC_PMEM3_MEMHIZ3_6

#define	FSMC_PMEM3_MEMHIZ3_7

#define	FSMC_PMEM4_MEMSET4

#define	FSMC_PMEM4_MEMSET4_0

#define	FSMC_PMEM4_MEMSET4_1

#define	FSMC_PMEM4_MEMSET4_2

#define	FSMC_PMEM4_MEMSET4_3

#define	FSMC_PMEM4_MEMSET4_4

#define	FSMC_PMEM4_MEMSET4_5

#define	FSMC_PMEM4_MEMSET4_6

#define	FSMC_PMEM4_MEMSET4_7

#define	FSMC_PMEM4_MEMWAIT4

#define	FSMC_PMEM4_MEMWAIT4_0

#define	FSMC_PMEM4_MEMWAIT4_1

#define	FSMC_PMEM4_MEMWAIT4_2

#define	FSMC_PMEM4_MEMWAIT4_3

#define	FSMC_PMEM4_MEMWAIT4_4

#define	FSMC_PMEM4_MEMWAIT4_5

#define	FSMC_PMEM4_MEMWAIT4_6

#define	FSMC_PMEM4_MEMWAIT4_7

#define	FSMC_PMEM4_MEMHOLD4

#define	FSMC_PMEM4_MEMHOLD4_0

#define	FSMC_PMEM4_MEMHOLD4_1

#define	FSMC_PMEM4_MEMHOLD4_2

#define	FSMC_PMEM4_MEMHOLD4_3

#define	FSMC_PMEM4_MEMHOLD4_4

#define	FSMC_PMEM4_MEMHOLD4_5

#define	FSMC_PMEM4_MEMHOLD4_6

#define	FSMC_PMEM4_MEMHOLD4_7

#define	FSMC_PMEM4_MEMHIZ4

#define	FSMC_PMEM4_MEMHIZ4_0

#define	FSMC_PMEM4_MEMHIZ4_1

#define	FSMC_PMEM4_MEMHIZ4_2

#define	FSMC_PMEM4_MEMHIZ4_3

#define	FSMC_PMEM4_MEMHIZ4_4

#define	FSMC_PMEM4_MEMHIZ4_5

#define	FSMC_PMEM4_MEMHIZ4_6

#define	FSMC_PMEM4_MEMHIZ4_7

#define	FSMC_PATT2_ATTSET2

#define	FSMC_PATT2_ATTSET2_0

#define	FSMC_PATT2_ATTSET2_1

#define	FSMC_PATT2_ATTSET2_2

#define	FSMC_PATT2_ATTSET2_3

#define	FSMC_PATT2_ATTSET2_4

#define	FSMC_PATT2_ATTSET2_5

#define	FSMC_PATT2_ATTSET2_6

#define	FSMC_PATT2_ATTSET2_7

#define	FSMC_PATT2_ATTWAIT2

#define	FSMC_PATT2_ATTWAIT2_0

#define	FSMC_PATT2_ATTWAIT2_1

#define	FSMC_PATT2_ATTWAIT2_2

#define	FSMC_PATT2_ATTWAIT2_3

#define	FSMC_PATT2_ATTWAIT2_4

#define	FSMC_PATT2_ATTWAIT2_5

#define	FSMC_PATT2_ATTWAIT2_6

#define	FSMC_PATT2_ATTWAIT2_7

#define	FSMC_PATT2_ATTHOLD2

#define	FSMC_PATT2_ATTHOLD2_0

#define	FSMC_PATT2_ATTHOLD2_1

#define	FSMC_PATT2_ATTHOLD2_2

#define	FSMC_PATT2_ATTHOLD2_3

#define	FSMC_PATT2_ATTHOLD2_4

#define	FSMC_PATT2_ATTHOLD2_5

#define	FSMC_PATT2_ATTHOLD2_6

#define	FSMC_PATT2_ATTHOLD2_7

#define	FSMC_PATT2_ATTHIZ2

#define	FSMC_PATT2_ATTHIZ2_0

#define	FSMC_PATT2_ATTHIZ2_1

#define	FSMC_PATT2_ATTHIZ2_2

#define	FSMC_PATT2_ATTHIZ2_3

#define	FSMC_PATT2_ATTHIZ2_4

#define	FSMC_PATT2_ATTHIZ2_5

#define	FSMC_PATT2_ATTHIZ2_6

#define	FSMC_PATT2_ATTHIZ2_7

#define	FSMC_PATT3_ATTSET3

#define	FSMC_PATT3_ATTSET3_0

#define	FSMC_PATT3_ATTSET3_1

#define	FSMC_PATT3_ATTSET3_2

#define	FSMC_PATT3_ATTSET3_3

#define	FSMC_PATT3_ATTSET3_4

#define	FSMC_PATT3_ATTSET3_5

#define	FSMC_PATT3_ATTSET3_6

#define	FSMC_PATT3_ATTSET3_7

#define	FSMC_PATT3_ATTWAIT3

#define	FSMC_PATT3_ATTWAIT3_0

#define	FSMC_PATT3_ATTWAIT3_1

#define	FSMC_PATT3_ATTWAIT3_2

#define	FSMC_PATT3_ATTWAIT3_3

#define	FSMC_PATT3_ATTWAIT3_4

#define	FSMC_PATT3_ATTWAIT3_5

#define	FSMC_PATT3_ATTWAIT3_6

#define	FSMC_PATT3_ATTWAIT3_7

#define	FSMC_PATT3_ATTHOLD3

#define	FSMC_PATT3_ATTHOLD3_0

#define	FSMC_PATT3_ATTHOLD3_1

#define	FSMC_PATT3_ATTHOLD3_2

#define	FSMC_PATT3_ATTHOLD3_3

#define	FSMC_PATT3_ATTHOLD3_4

#define	FSMC_PATT3_ATTHOLD3_5

#define	FSMC_PATT3_ATTHOLD3_6

#define	FSMC_PATT3_ATTHOLD3_7

#define	FSMC_PATT3_ATTHIZ3

#define	FSMC_PATT3_ATTHIZ3_0

#define	FSMC_PATT3_ATTHIZ3_1

#define	FSMC_PATT3_ATTHIZ3_2

#define	FSMC_PATT3_ATTHIZ3_3

#define	FSMC_PATT3_ATTHIZ3_4

#define	FSMC_PATT3_ATTHIZ3_5

#define	FSMC_PATT3_ATTHIZ3_6

#define	FSMC_PATT3_ATTHIZ3_7

#define	FSMC_PATT4_ATTSET4

#define	FSMC_PATT4_ATTSET4_0

#define	FSMC_PATT4_ATTSET4_1

#define	FSMC_PATT4_ATTSET4_2

#define	FSMC_PATT4_ATTSET4_3

#define	FSMC_PATT4_ATTSET4_4

#define	FSMC_PATT4_ATTSET4_5

#define	FSMC_PATT4_ATTSET4_6

#define	FSMC_PATT4_ATTSET4_7

#define	FSMC_PATT4_ATTWAIT4

#define	FSMC_PATT4_ATTWAIT4_0

#define	FSMC_PATT4_ATTWAIT4_1

#define	FSMC_PATT4_ATTWAIT4_2

#define	FSMC_PATT4_ATTWAIT4_3

#define	FSMC_PATT4_ATTWAIT4_4

#define	FSMC_PATT4_ATTWAIT4_5

#define	FSMC_PATT4_ATTWAIT4_6

#define	FSMC_PATT4_ATTWAIT4_7

#define	FSMC_PATT4_ATTHOLD4

#define	FSMC_PATT4_ATTHOLD4_0

#define	FSMC_PATT4_ATTHOLD4_1

#define	FSMC_PATT4_ATTHOLD4_2

#define	FSMC_PATT4_ATTHOLD4_3

#define	FSMC_PATT4_ATTHOLD4_4

#define	FSMC_PATT4_ATTHOLD4_5

#define	FSMC_PATT4_ATTHOLD4_6

#define	FSMC_PATT4_ATTHOLD4_7

#define	FSMC_PATT4_ATTHIZ4

#define	FSMC_PATT4_ATTHIZ4_0

#define	FSMC_PATT4_ATTHIZ4_1

#define	FSMC_PATT4_ATTHIZ4_2

#define	FSMC_PATT4_ATTHIZ4_3

#define	FSMC_PATT4_ATTHIZ4_4

#define	FSMC_PATT4_ATTHIZ4_5

#define	FSMC_PATT4_ATTHIZ4_6

#define	FSMC_PATT4_ATTHIZ4_7

#define	FSMC_PIO4_IOSET4

#define	FSMC_PIO4_IOSET4_0

#define	FSMC_PIO4_IOSET4_1

#define	FSMC_PIO4_IOSET4_2

#define	FSMC_PIO4_IOSET4_3

#define	FSMC_PIO4_IOSET4_4

#define	FSMC_PIO4_IOSET4_5

#define	FSMC_PIO4_IOSET4_6

#define	FSMC_PIO4_IOSET4_7

#define	FSMC_PIO4_IOWAIT4

#define	FSMC_PIO4_IOWAIT4_0

#define	FSMC_PIO4_IOWAIT4_1

#define	FSMC_PIO4_IOWAIT4_2

#define	FSMC_PIO4_IOWAIT4_3

#define	FSMC_PIO4_IOWAIT4_4

#define	FSMC_PIO4_IOWAIT4_5

#define	FSMC_PIO4_IOWAIT4_6

#define	FSMC_PIO4_IOWAIT4_7

#define	FSMC_PIO4_IOHOLD4

#define	FSMC_PIO4_IOHOLD4_0

#define	FSMC_PIO4_IOHOLD4_1

#define	FSMC_PIO4_IOHOLD4_2

#define	FSMC_PIO4_IOHOLD4_3

#define	FSMC_PIO4_IOHOLD4_4

#define	FSMC_PIO4_IOHOLD4_5

#define	FSMC_PIO4_IOHOLD4_6

#define	FSMC_PIO4_IOHOLD4_7

#define	FSMC_PIO4_IOHIZ4

#define	FSMC_PIO4_IOHIZ4_0

#define	FSMC_PIO4_IOHIZ4_1

#define	FSMC_PIO4_IOHIZ4_2

#define	FSMC_PIO4_IOHIZ4_3

#define	FSMC_PIO4_IOHIZ4_4

#define	FSMC_PIO4_IOHIZ4_5

#define	FSMC_PIO4_IOHIZ4_6

#define	FSMC_PIO4_IOHIZ4_7

#define	FSMC_ECCR2_ECC2

#define	FSMC_ECCR3_ECC3

#define	I2C_CR1_PE

#define	I2C_CR1_SMBUS

#define	I2C_CR1_SMBTYPE

#define	I2C_CR1_ENARP

#define	I2C_CR1_ENPEC

#define	I2C_CR1_ENGC

#define	I2C_CR1_NOSTRETCH

#define	I2C_CR1_START

#define	I2C_CR1_STOP

#define	I2C_CR1_ACK

#define	I2C_CR1_POS

#define	I2C_CR1_PEC

#define	I2C_CR1_ALERT

#define	I2C_CR1_SWRST

#define	I2C_CR2_FREQ

#define	I2C_CR2_FREQ_0

#define	I2C_CR2_FREQ_1

#define	I2C_CR2_FREQ_2

#define	I2C_CR2_FREQ_3

#define	I2C_CR2_FREQ_4

#define	I2C_CR2_FREQ_5

#define	I2C_CR2_ITERREN

#define	I2C_CR2_ITEVTEN

#define	I2C_CR2_ITBUFEN

#define	I2C_CR2_DMAEN

#define	I2C_CR2_LAST

#define	I2C_OAR1_ADD1_7

#define	I2C_OAR1_ADD8_9

#define	I2C_OAR1_ADD0

#define	I2C_OAR1_ADD1

#define	I2C_OAR1_ADD2

#define	I2C_OAR1_ADD3

#define	I2C_OAR1_ADD4

#define	I2C_OAR1_ADD5

#define	I2C_OAR1_ADD6

#define	I2C_OAR1_ADD7

#define	I2C_OAR1_ADD8

#define	I2C_OAR1_ADD9

#define	I2C_OAR1_ADDMODE

#define	I2C_OAR2_ENDUAL

#define	I2C_OAR2_ADD2

#define	I2C_DR_DR

#define	I2C_SR1_SB

#define	I2C_SR1_ADDR

#define	I2C_SR1_BTF

#define	I2C_SR1_ADD10

#define	I2C_SR1_STOPF

#define	I2C_SR1_RXNE

#define	I2C_SR1_TXE

#define	I2C_SR1_BERR

#define	I2C_SR1_ARLO

#define	I2C_SR1_AF

#define	I2C_SR1_OVR

#define	I2C_SR1_PECERR

#define	I2C_SR1_TIMEOUT

#define	I2C_SR1_SMBALERT

#define	I2C_SR2_MSL

#define	I2C_SR2_BUSY

#define	I2C_SR2_TRA

#define	I2C_SR2_GENCALL

#define	I2C_SR2_SMBDEFAULT

#define	I2C_SR2_SMBHOST

#define	I2C_SR2_DUALF

#define	I2C_SR2_PEC

#define	I2C_CCR_CCR

#define	I2C_CCR_DUTY

#define	I2C_CCR_FS

#define	I2C_TRISE_TRISE

#define	IWDG_KR_KEY

#define	IWDG_PR_PR

#define	IWDG_PR_PR_0

#define	IWDG_PR_PR_1

#define	IWDG_PR_PR_2

#define	IWDG_RLR_RL

#define	IWDG_SR_PVU

#define	IWDG_SR_RVU

#define	PWR_CR_LPDS

#define	PWR_CR_PDDS

#define	PWR_CR_CWUF

#define	PWR_CR_CSBF

#define	PWR_CR_PVDE

#define	PWR_CR_PLS

#define	PWR_CR_PLS_0

#define	PWR_CR_PLS_1

#define	PWR_CR_PLS_2

#define	PWR_CR_PLS_LEV0

#define	PWR_CR_PLS_LEV1

#define	PWR_CR_PLS_LEV2

#define	PWR_CR_PLS_LEV3

#define	PWR_CR_PLS_LEV4

#define	PWR_CR_PLS_LEV5

#define	PWR_CR_PLS_LEV6

#define	PWR_CR_PLS_LEV7

#define	PWR_CR_DBP

#define	PWR_CR_FPDS

#define	PWR_CR_VOS

#define	PWR_CSR_WUF

#define	PWR_CSR_SBF

#define	PWR_CSR_PVDO

#define	PWR_CSR_BRR

#define	PWR_CSR_EWUP

#define	PWR_CSR_BRE

#define	PWR_CSR_VOSRDY

#define	RCC_CR_HSITRIM_0

#define	RCC_CR_HSITRIM_1

#define	RCC_CR_HSITRIM_2

#define	RCC_CR_HSITRIM_3

#define	RCC_CR_HSITRIM_4

#define	RCC_CR_HSICAL_0

#define	RCC_CR_HSICAL_1

#define	RCC_CR_HSICAL_2

#define	RCC_CR_HSICAL_3

#define	RCC_CR_HSICAL_4

#define	RCC_CR_HSICAL_5

#define	RCC_CR_HSICAL_6

#define	RCC_CR_HSICAL_7

#define	RCC_CFGR_SW

#define	RCC_CFGR_SW_0

#define	RCC_CFGR_SW_1

#define	RCC_CFGR_SW_HSI

#define	RCC_CFGR_SW_HSE

#define	RCC_CFGR_SW_PLL

#define	RCC_CFGR_SWS

#define	RCC_CFGR_SWS_0

#define	RCC_CFGR_SWS_1

#define	RCC_CFGR_SWS_HSI

#define	RCC_CFGR_SWS_HSE

#define	RCC_CFGR_SWS_PLL

#define	RCC_CFGR_HPRE

#define	RCC_CFGR_HPRE_0

#define	RCC_CFGR_HPRE_1

#define	RCC_CFGR_HPRE_2

#define	RCC_CFGR_HPRE_3

#define	RCC_CFGR_HPRE_DIV1

#define	RCC_CFGR_HPRE_DIV2

#define	RCC_CFGR_HPRE_DIV4

#define	RCC_CFGR_HPRE_DIV8

#define	RCC_CFGR_HPRE_DIV16

#define	RCC_CFGR_HPRE_DIV64

#define	RCC_CFGR_HPRE_DIV128

#define	RCC_CFGR_HPRE_DIV256

#define	RCC_CFGR_HPRE_DIV512

#define	RCC_CFGR_PPRE1

#define	RCC_CFGR_PPRE1_0

#define	RCC_CFGR_PPRE1_1

#define	RCC_CFGR_PPRE1_2

#define	RCC_CFGR_PPRE1_DIV1

#define	RCC_CFGR_PPRE1_DIV2

#define	RCC_CFGR_PPRE1_DIV4

#define	RCC_CFGR_PPRE1_DIV8

#define	RCC_CFGR_PPRE1_DIV16

#define	RCC_CFGR_PPRE2

#define	RCC_CFGR_PPRE2_0

#define	RCC_CFGR_PPRE2_1

#define	RCC_CFGR_PPRE2_2

#define	RCC_CFGR_PPRE2_DIV1

#define	RCC_CFGR_PPRE2_DIV2

#define	RCC_CFGR_PPRE2_DIV4

#define	RCC_CFGR_PPRE2_DIV8

#define	RCC_CFGR_PPRE2_DIV16

#define	RCC_CFGR_RTCPRE_4

#define	SDIO_POWER_PWRCTRL

#define	SDIO_POWER_PWRCTRL_0

#define	SDIO_POWER_PWRCTRL_1

#define	SDIO_CLKCR_CLKDIV

#define	SDIO_CLKCR_CLKEN

#define	SDIO_CLKCR_PWRSAV

#define	SDIO_CLKCR_BYPASS

#define	SDIO_CLKCR_WIDBUS

#define	SDIO_CLKCR_WIDBUS_0

#define	SDIO_CLKCR_WIDBUS_1

#define	SDIO_CLKCR_NEGEDGE

#define	SDIO_CLKCR_HWFC_EN

#define	SDIO_ARG_CMDARG

#define	SDIO_CMD_CMDINDEX

#define	SDIO_CMD_WAITRESP

#define	SDIO_CMD_WAITRESP_0

#define	SDIO_CMD_WAITRESP_1

#define	SDIO_CMD_WAITINT

#define	SDIO_CMD_WAITPEND

#define	SDIO_CMD_CPSMEN

#define	SDIO_CMD_SDIOSUSPEND

#define	SDIO_CMD_ENCMDCOMPL

#define	SDIO_CMD_NIEN

#define	SDIO_CMD_CEATACMD

#define	SDIO_RESPCMD_RESPCMD

#define	SDIO_RESP0_CARDSTATUS0

#define	SDIO_RESP1_CARDSTATUS1

#define	SDIO_RESP2_CARDSTATUS2

#define	SDIO_RESP3_CARDSTATUS3

#define	SDIO_RESP4_CARDSTATUS4

#define	SDIO_DTIMER_DATATIME

#define	SDIO_DLEN_DATALENGTH

#define	SDIO_DCTRL_DTEN

#define	SDIO_DCTRL_DTDIR

#define	SDIO_DCTRL_DTMODE

#define	SDIO_DCTRL_DMAEN

#define	SDIO_DCTRL_DBLOCKSIZE

#define	SDIO_DCTRL_DBLOCKSIZE_0

#define	SDIO_DCTRL_DBLOCKSIZE_1

#define	SDIO_DCTRL_DBLOCKSIZE_2

#define	SDIO_DCTRL_DBLOCKSIZE_3

#define	SDIO_DCTRL_RWSTART

#define	SDIO_DCTRL_RWSTOP

#define	SDIO_DCTRL_RWMOD

#define	SDIO_DCTRL_SDIOEN

#define	SDIO_DCOUNT_DATACOUNT

#define	SDIO_STA_CCRCFAIL

#define	SDIO_STA_DCRCFAIL

#define	SDIO_STA_CTIMEOUT

#define	SDIO_STA_DTIMEOUT

#define	SDIO_STA_TXUNDERR

#define	SDIO_STA_RXOVERR

#define	SDIO_STA_CMDREND

#define	SDIO_STA_CMDSENT

#define	SDIO_STA_DATAEND

#define	SDIO_STA_STBITERR

#define	SDIO_STA_DBCKEND

#define	SDIO_STA_CMDACT

#define	SDIO_STA_TXACT

#define	SDIO_STA_RXACT

#define	SDIO_STA_TXFIFOHE

#define	SDIO_STA_RXFIFOHF

#define	SDIO_STA_TXFIFOF

#define	SDIO_STA_RXFIFOF

#define	SDIO_STA_TXFIFOE

#define	SDIO_STA_RXFIFOE

#define	SDIO_STA_TXDAVL

#define	SDIO_STA_RXDAVL

#define	SDIO_STA_SDIOIT

#define	SDIO_STA_CEATAEND

#define	SDIO_ICR_CCRCFAILC

#define	SDIO_ICR_DCRCFAILC

#define	SDIO_ICR_CTIMEOUTC

#define	SDIO_ICR_DTIMEOUTC

#define	SDIO_ICR_TXUNDERRC

#define	SDIO_ICR_RXOVERRC

#define	SDIO_ICR_CMDRENDC

#define	SDIO_ICR_CMDSENTC

#define	SDIO_ICR_DATAENDC

#define	SDIO_ICR_STBITERRC

#define	SDIO_ICR_DBCKENDC

#define	SDIO_ICR_SDIOITC

#define	SDIO_ICR_CEATAENDC

#define	SDIO_MASK_CCRCFAILIE

#define	SDIO_MASK_DCRCFAILIE

#define	SDIO_MASK_CTIMEOUTIE

#define	SDIO_MASK_DTIMEOUTIE

#define	SDIO_MASK_TXUNDERRIE

#define	SDIO_MASK_RXOVERRIE

#define	SDIO_MASK_CMDRENDIE

#define	SDIO_MASK_CMDSENTIE

#define	SDIO_MASK_DATAENDIE

#define	SDIO_MASK_STBITERRIE

#define	SDIO_MASK_DBCKENDIE

#define	SDIO_MASK_CMDACTIE

#define	SDIO_MASK_TXACTIE

#define	SDIO_MASK_RXACTIE

#define	SDIO_MASK_TXFIFOHEIE

#define	SDIO_MASK_RXFIFOHFIE

#define	SDIO_MASK_TXFIFOFIE

#define	SDIO_MASK_RXFIFOFIE

#define	SDIO_MASK_TXFIFOEIE

#define	SDIO_MASK_RXFIFOEIE

#define	SDIO_MASK_TXDAVLIE

#define	SDIO_MASK_RXDAVLIE

#define	SDIO_MASK_SDIOITIE

#define	SDIO_MASK_CEATAENDIE

#define	SDIO_FIFOCNT_FIFOCOUNT

#define	SDIO_FIFO_FIFODATA

#define	SPI_CR1_CPHA

#define	SPI_CR1_CPOL

#define	SPI_CR1_MSTR

#define	SPI_CR1_BR

#define	SPI_CR1_BR_0

#define	SPI_CR1_BR_1

#define	SPI_CR1_BR_2

#define	SPI_CR1_SPE

#define	SPI_CR1_LSBFIRST

#define	SPI_CR1_SSI

#define	SPI_CR1_SSM

#define	SPI_CR1_RXONLY

#define	SPI_CR1_DFF

#define	SPI_CR1_CRCNEXT

#define	SPI_CR1_CRCEN

#define	SPI_CR1_BIDIOE

#define	SPI_CR1_BIDIMODE

#define	SPI_CR2_RXDMAEN

#define	SPI_CR2_TXDMAEN

#define	SPI_CR2_SSOE

#define	SPI_CR2_ERRIE

#define	SPI_CR2_RXNEIE

#define	SPI_CR2_TXEIE

#define	SPI_SR_RXNE

#define	SPI_SR_TXE

#define	SPI_SR_CHSIDE

#define	SPI_SR_UDR

#define	SPI_SR_CRCERR

#define	SPI_SR_MODF

#define	SPI_SR_OVR

#define	SPI_SR_BSY

#define	SPI_DR_DR

#define	SPI_CRCPR_CRCPOLY

#define	SPI_RXCRCR_RXCRC

#define	SPI_TXCRCR_TXCRC

#define	SPI_I2SCFGR_CHLEN

#define	SPI_I2SCFGR_DATLEN

#define	SPI_I2SCFGR_DATLEN_0

#define	SPI_I2SCFGR_DATLEN_1

#define	SPI_I2SCFGR_CKPOL

#define	SPI_I2SCFGR_I2SSTD

#define	SPI_I2SCFGR_I2SSTD_0

#define	SPI_I2SCFGR_I2SSTD_1

#define	SPI_I2SCFGR_PCMSYNC

#define	SPI_I2SCFGR_I2SCFG

#define	SPI_I2SCFGR_I2SCFG_0

#define	SPI_I2SCFGR_I2SCFG_1

#define	SPI_I2SCFGR_I2SE

#define	SPI_I2SCFGR_I2SMOD

#define	SPI_I2SPR_I2SDIV

#define	SPI_I2SPR_ODD

#define	SPI_I2SPR_MCKOE

#define	SYSCFG_MEMRMP_MEM_MODE

#define	SYSCFG_PMC_MII_RMII_SEL

#define	SYSCFG_EXTICR1_EXTI0

#define	SYSCFG_EXTICR1_EXTI1

#define	SYSCFG_EXTICR1_EXTI2

#define	SYSCFG_EXTICR1_EXTI3

#define	SYSCFG_EXTICR1_EXTI0_PA
	EXTI0 configuration. More...

#define	SYSCFG_EXTICR1_EXTI0_PB

#define	SYSCFG_EXTICR1_EXTI0_PC

#define	SYSCFG_EXTICR1_EXTI0_PD

#define	SYSCFG_EXTICR1_EXTI0_PE

#define	SYSCFG_EXTICR1_EXTI0_PF

#define	SYSCFG_EXTICR1_EXTI0_PG

#define	SYSCFG_EXTICR1_EXTI0_PH

#define	SYSCFG_EXTICR1_EXTI0_PI

#define	SYSCFG_EXTICR1_EXTI1_PA
	EXTI1 configuration. More...

#define	SYSCFG_EXTICR1_EXTI1_PB

#define	SYSCFG_EXTICR1_EXTI1_PC

#define	SYSCFG_EXTICR1_EXTI1_PD

#define	SYSCFG_EXTICR1_EXTI1_PE

#define	SYSCFG_EXTICR1_EXTI1_PF

#define	SYSCFG_EXTICR1_EXTI1_PG

#define	SYSCFG_EXTICR1_EXTI1_PH

#define	SYSCFG_EXTICR1_EXTI1_PI

#define	SYSCFG_EXTICR1_EXTI2_PA
	EXTI2 configuration. More...

#define	SYSCFG_EXTICR1_EXTI2_PB

#define	SYSCFG_EXTICR1_EXTI2_PC

#define	SYSCFG_EXTICR1_EXTI2_PD

#define	SYSCFG_EXTICR1_EXTI2_PE

#define	SYSCFG_EXTICR1_EXTI2_PF

#define	SYSCFG_EXTICR1_EXTI2_PG

#define	SYSCFG_EXTICR1_EXTI2_PH

#define	SYSCFG_EXTICR1_EXTI2_PI

#define	SYSCFG_EXTICR1_EXTI3_PA
	EXTI3 configuration. More...

#define	SYSCFG_EXTICR1_EXTI3_PB

#define	SYSCFG_EXTICR1_EXTI3_PC

#define	SYSCFG_EXTICR1_EXTI3_PD

#define	SYSCFG_EXTICR1_EXTI3_PE

#define	SYSCFG_EXTICR1_EXTI3_PF

#define	SYSCFG_EXTICR1_EXTI3_PG

#define	SYSCFG_EXTICR1_EXTI3_PH

#define	SYSCFG_EXTICR1_EXTI3_PI

#define	SYSCFG_EXTICR2_EXTI4

#define	SYSCFG_EXTICR2_EXTI5

#define	SYSCFG_EXTICR2_EXTI6

#define	SYSCFG_EXTICR2_EXTI7

#define	SYSCFG_EXTICR2_EXTI4_PA
	EXTI4 configuration. More...

#define	SYSCFG_EXTICR2_EXTI4_PB

#define	SYSCFG_EXTICR2_EXTI4_PC

#define	SYSCFG_EXTICR2_EXTI4_PD

#define	SYSCFG_EXTICR2_EXTI4_PE

#define	SYSCFG_EXTICR2_EXTI4_PF

#define	SYSCFG_EXTICR2_EXTI4_PG

#define	SYSCFG_EXTICR2_EXTI4_PH

#define	SYSCFG_EXTICR2_EXTI4_PI

#define	SYSCFG_EXTICR2_EXTI5_PA
	EXTI5 configuration. More...

#define	SYSCFG_EXTICR2_EXTI5_PB

#define	SYSCFG_EXTICR2_EXTI5_PC

#define	SYSCFG_EXTICR2_EXTI5_PD

#define	SYSCFG_EXTICR2_EXTI5_PE

#define	SYSCFG_EXTICR2_EXTI5_PF

#define	SYSCFG_EXTICR2_EXTI5_PG

#define	SYSCFG_EXTICR2_EXTI5_PH

#define	SYSCFG_EXTICR2_EXTI5_PI

#define	SYSCFG_EXTICR2_EXTI6_PA
	EXTI6 configuration. More...

#define	SYSCFG_EXTICR2_EXTI6_PB

#define	SYSCFG_EXTICR2_EXTI6_PC

#define	SYSCFG_EXTICR2_EXTI6_PD

#define	SYSCFG_EXTICR2_EXTI6_PE

#define	SYSCFG_EXTICR2_EXTI6_PF

#define	SYSCFG_EXTICR2_EXTI6_PG

#define	SYSCFG_EXTICR2_EXTI6_PH

#define	SYSCFG_EXTICR2_EXTI6_PI

#define	SYSCFG_EXTICR2_EXTI7_PA
	EXTI7 configuration. More...

#define	SYSCFG_EXTICR2_EXTI7_PB

#define	SYSCFG_EXTICR2_EXTI7_PC

#define	SYSCFG_EXTICR2_EXTI7_PD

#define	SYSCFG_EXTICR2_EXTI7_PE

#define	SYSCFG_EXTICR2_EXTI7_PF

#define	SYSCFG_EXTICR2_EXTI7_PG

#define	SYSCFG_EXTICR2_EXTI7_PH

#define	SYSCFG_EXTICR2_EXTI7_PI

#define	SYSCFG_EXTICR3_EXTI8

#define	SYSCFG_EXTICR3_EXTI9

#define	SYSCFG_EXTICR3_EXTI10

#define	SYSCFG_EXTICR3_EXTI11

#define	SYSCFG_EXTICR3_EXTI8_PA
	EXTI8 configuration. More...

#define	SYSCFG_EXTICR3_EXTI8_PB

#define	SYSCFG_EXTICR3_EXTI8_PC

#define	SYSCFG_EXTICR3_EXTI8_PD

#define	SYSCFG_EXTICR3_EXTI8_PE

#define	SYSCFG_EXTICR3_EXTI8_PF

#define	SYSCFG_EXTICR3_EXTI8_PG

#define	SYSCFG_EXTICR3_EXTI8_PH

#define	SYSCFG_EXTICR3_EXTI8_PI

#define	SYSCFG_EXTICR3_EXTI9_PA
	EXTI9 configuration. More...

#define	SYSCFG_EXTICR3_EXTI9_PB

#define	SYSCFG_EXTICR3_EXTI9_PC

#define	SYSCFG_EXTICR3_EXTI9_PD

#define	SYSCFG_EXTICR3_EXTI9_PE

#define	SYSCFG_EXTICR3_EXTI9_PF

#define	SYSCFG_EXTICR3_EXTI9_PG

#define	SYSCFG_EXTICR3_EXTI9_PH

#define	SYSCFG_EXTICR3_EXTI9_PI

#define	SYSCFG_EXTICR3_EXTI10_PA
	EXTI10 configuration. More...

#define	SYSCFG_EXTICR3_EXTI10_PB

#define	SYSCFG_EXTICR3_EXTI10_PC

#define	SYSCFG_EXTICR3_EXTI10_PD

#define	SYSCFG_EXTICR3_EXTI10_PE

#define	SYSCFG_EXTICR3_EXTI10_PF

#define	SYSCFG_EXTICR3_EXTI10_PG

#define	SYSCFG_EXTICR3_EXTI10_PH

#define	SYSCFG_EXTICR3_EXTI10_PI

#define	SYSCFG_EXTICR3_EXTI11_PA
	EXTI11 configuration. More...

#define	SYSCFG_EXTICR3_EXTI11_PB

#define	SYSCFG_EXTICR3_EXTI11_PC

#define	SYSCFG_EXTICR3_EXTI11_PD

#define	SYSCFG_EXTICR3_EXTI11_PE

#define	SYSCFG_EXTICR3_EXTI11_PF

#define	SYSCFG_EXTICR3_EXTI11_PG

#define	SYSCFG_EXTICR3_EXTI11_PH

#define	SYSCFG_EXTICR3_EXTI11_PI

#define	SYSCFG_EXTICR4_EXTI12

#define	SYSCFG_EXTICR4_EXTI13

#define	SYSCFG_EXTICR4_EXTI14

#define	SYSCFG_EXTICR4_EXTI15

#define	SYSCFG_EXTICR4_EXTI12_PA
	EXTI12 configuration. More...

#define	SYSCFG_EXTICR4_EXTI12_PB

#define	SYSCFG_EXTICR4_EXTI12_PC

#define	SYSCFG_EXTICR4_EXTI12_PD

#define	SYSCFG_EXTICR4_EXTI12_PE

#define	SYSCFG_EXTICR4_EXTI12_PF

#define	SYSCFG_EXTICR4_EXTI12_PG

#define	SYSCFG_EXTICR3_EXTI12_PH

#define	SYSCFG_EXTICR4_EXTI13_PA
	EXTI13 configuration. More...

#define	SYSCFG_EXTICR4_EXTI13_PB

#define	SYSCFG_EXTICR4_EXTI13_PC

#define	SYSCFG_EXTICR4_EXTI13_PD

#define	SYSCFG_EXTICR4_EXTI13_PE

#define	SYSCFG_EXTICR4_EXTI13_PF

#define	SYSCFG_EXTICR4_EXTI13_PG

#define	SYSCFG_EXTICR3_EXTI13_PH

#define	SYSCFG_EXTICR4_EXTI14_PA
	EXTI14 configuration. More...

#define	SYSCFG_EXTICR4_EXTI14_PB

#define	SYSCFG_EXTICR4_EXTI14_PC

#define	SYSCFG_EXTICR4_EXTI14_PD

#define	SYSCFG_EXTICR4_EXTI14_PE

#define	SYSCFG_EXTICR4_EXTI14_PF

#define	SYSCFG_EXTICR4_EXTI14_PG

#define	SYSCFG_EXTICR3_EXTI14_PH

#define	SYSCFG_EXTICR4_EXTI15_PA
	EXTI15 configuration. More...

#define	SYSCFG_EXTICR4_EXTI15_PB

#define	SYSCFG_EXTICR4_EXTI15_PC

#define	SYSCFG_EXTICR4_EXTI15_PD

#define	SYSCFG_EXTICR4_EXTI15_PE

#define	SYSCFG_EXTICR4_EXTI15_PF

#define	SYSCFG_EXTICR4_EXTI15_PG

#define	SYSCFG_EXTICR3_EXTI15_PH

#define	SYSCFG_CMPCR_CMP_PD

#define	SYSCFG_CMPCR_READY

#define	TIM_CR1_CEN

#define	TIM_CR1_UDIS

#define	TIM_CR1_URS

#define	TIM_CR1_OPM

#define	TIM_CR1_DIR

#define	TIM_CR1_CMS

#define	TIM_CR1_CMS_0

#define	TIM_CR1_CMS_1

#define	TIM_CR1_ARPE

#define	TIM_CR1_CKD

#define	TIM_CR1_CKD_0

#define	TIM_CR1_CKD_1

#define	TIM_CR2_CCPC

#define	TIM_CR2_CCUS

#define	TIM_CR2_CCDS

#define	TIM_CR2_MMS

#define	TIM_CR2_MMS_0

#define	TIM_CR2_MMS_1

#define	TIM_CR2_MMS_2

#define	TIM_CR2_TI1S

#define	TIM_CR2_OIS1

#define	TIM_CR2_OIS1N

#define	TIM_CR2_OIS2

#define	TIM_CR2_OIS2N

#define	TIM_CR2_OIS3

#define	TIM_CR2_OIS3N

#define	TIM_CR2_OIS4

#define	TIM_SMCR_SMS

#define	TIM_SMCR_SMS_0

#define	TIM_SMCR_SMS_1

#define	TIM_SMCR_SMS_2

#define	TIM_SMCR_TS

#define	TIM_SMCR_TS_0

#define	TIM_SMCR_TS_1

#define	TIM_SMCR_TS_2

#define	TIM_SMCR_MSM

#define	TIM_SMCR_ETF

#define	TIM_SMCR_ETF_0

#define	TIM_SMCR_ETF_1

#define	TIM_SMCR_ETF_2

#define	TIM_SMCR_ETF_3

#define	TIM_SMCR_ETPS

#define	TIM_SMCR_ETPS_0

#define	TIM_SMCR_ETPS_1

#define	TIM_SMCR_ECE

#define	TIM_SMCR_ETP

#define	TIM_DIER_UIE

#define	TIM_DIER_CC1IE

#define	TIM_DIER_CC2IE

#define	TIM_DIER_CC3IE

#define	TIM_DIER_CC4IE

#define	TIM_DIER_COMIE

#define	TIM_DIER_TIE

#define	TIM_DIER_BIE

#define	TIM_DIER_UDE

#define	TIM_DIER_CC1DE

#define	TIM_DIER_CC2DE

#define	TIM_DIER_CC3DE

#define	TIM_DIER_CC4DE

#define	TIM_DIER_COMDE

#define	TIM_DIER_TDE

#define	TIM_SR_UIF

#define	TIM_SR_CC1IF

#define	TIM_SR_CC2IF

#define	TIM_SR_CC3IF

#define	TIM_SR_CC4IF

#define	TIM_SR_COMIF

#define	TIM_SR_TIF

#define	TIM_SR_BIF

#define	TIM_SR_CC1OF

#define	TIM_SR_CC2OF

#define	TIM_SR_CC3OF

#define	TIM_SR_CC4OF

#define	TIM_EGR_UG

#define	TIM_EGR_CC1G

#define	TIM_EGR_CC2G

#define	TIM_EGR_CC3G

#define	TIM_EGR_CC4G

#define	TIM_EGR_COMG

#define	TIM_EGR_TG

#define	TIM_EGR_BG

#define	TIM_CCMR1_CC1S

#define	TIM_CCMR1_CC1S_0

#define	TIM_CCMR1_CC1S_1

#define	TIM_CCMR1_OC1FE

#define	TIM_CCMR1_OC1PE

#define	TIM_CCMR1_OC1M

#define	TIM_CCMR1_OC1M_0

#define	TIM_CCMR1_OC1M_1

#define	TIM_CCMR1_OC1M_2

#define	TIM_CCMR1_OC1CE

#define	TIM_CCMR1_CC2S

#define	TIM_CCMR1_CC2S_0

#define	TIM_CCMR1_CC2S_1

#define	TIM_CCMR1_OC2FE

#define	TIM_CCMR1_OC2PE

#define	TIM_CCMR1_OC2M

#define	TIM_CCMR1_OC2M_0

#define	TIM_CCMR1_OC2M_1

#define	TIM_CCMR1_OC2M_2

#define	TIM_CCMR1_OC2CE

#define	TIM_CCMR1_IC1PSC

#define	TIM_CCMR1_IC1PSC_0

#define	TIM_CCMR1_IC1PSC_1

#define	TIM_CCMR1_IC1F

#define	TIM_CCMR1_IC1F_0

#define	TIM_CCMR1_IC1F_1

#define	TIM_CCMR1_IC1F_2

#define	TIM_CCMR1_IC1F_3

#define	TIM_CCMR1_IC2PSC

#define	TIM_CCMR1_IC2PSC_0

#define	TIM_CCMR1_IC2PSC_1

#define	TIM_CCMR1_IC2F

#define	TIM_CCMR1_IC2F_0

#define	TIM_CCMR1_IC2F_1

#define	TIM_CCMR1_IC2F_2

#define	TIM_CCMR1_IC2F_3

#define	TIM_CCMR2_CC3S

#define	TIM_CCMR2_CC3S_0

#define	TIM_CCMR2_CC3S_1

#define	TIM_CCMR2_OC3FE

#define	TIM_CCMR2_OC3PE

#define	TIM_CCMR2_OC3M

#define	TIM_CCMR2_OC3M_0

#define	TIM_CCMR2_OC3M_1

#define	TIM_CCMR2_OC3M_2

#define	TIM_CCMR2_OC3CE

#define	TIM_CCMR2_CC4S

#define	TIM_CCMR2_CC4S_0

#define	TIM_CCMR2_CC4S_1

#define	TIM_CCMR2_OC4FE

#define	TIM_CCMR2_OC4PE

#define	TIM_CCMR2_OC4M

#define	TIM_CCMR2_OC4M_0

#define	TIM_CCMR2_OC4M_1

#define	TIM_CCMR2_OC4M_2

#define	TIM_CCMR2_OC4CE

#define	TIM_CCMR2_IC3PSC

#define	TIM_CCMR2_IC3PSC_0

#define	TIM_CCMR2_IC3PSC_1

#define	TIM_CCMR2_IC3F

#define	TIM_CCMR2_IC3F_0

#define	TIM_CCMR2_IC3F_1

#define	TIM_CCMR2_IC3F_2

#define	TIM_CCMR2_IC3F_3

#define	TIM_CCMR2_IC4PSC

#define	TIM_CCMR2_IC4PSC_0

#define	TIM_CCMR2_IC4PSC_1

#define	TIM_CCMR2_IC4F

#define	TIM_CCMR2_IC4F_0

#define	TIM_CCMR2_IC4F_1

#define	TIM_CCMR2_IC4F_2

#define	TIM_CCMR2_IC4F_3

#define	TIM_CCER_CC1E

#define	TIM_CCER_CC1P

#define	TIM_CCER_CC1NE

#define	TIM_CCER_CC1NP

#define	TIM_CCER_CC2E

#define	TIM_CCER_CC2P

#define	TIM_CCER_CC2NE

#define	TIM_CCER_CC2NP

#define	TIM_CCER_CC3E

#define	TIM_CCER_CC3P

#define	TIM_CCER_CC3NE

#define	TIM_CCER_CC3NP

#define	TIM_CCER_CC4E

#define	TIM_CCER_CC4P

#define	TIM_CCER_CC4NP

#define	TIM_CNT_CNT

#define	TIM_PSC_PSC

#define	TIM_ARR_ARR

#define	TIM_RCR_REP

#define	TIM_CCR1_CCR1

#define	TIM_CCR2_CCR2

#define	TIM_CCR3_CCR3

#define	TIM_CCR4_CCR4

#define	TIM_BDTR_DTG

#define	TIM_BDTR_DTG_0

#define	TIM_BDTR_DTG_1

#define	TIM_BDTR_DTG_2

#define	TIM_BDTR_DTG_3

#define	TIM_BDTR_DTG_4

#define	TIM_BDTR_DTG_5

#define	TIM_BDTR_DTG_6

#define	TIM_BDTR_DTG_7

#define	TIM_BDTR_LOCK

#define	TIM_BDTR_LOCK_0

#define	TIM_BDTR_LOCK_1

#define	TIM_BDTR_OSSI

#define	TIM_BDTR_OSSR

#define	TIM_BDTR_BKE

#define	TIM_BDTR_BKP

#define	TIM_BDTR_AOE

#define	TIM_BDTR_MOE

#define	TIM_DCR_DBA

#define	TIM_DCR_DBA_0

#define	TIM_DCR_DBA_1

#define	TIM_DCR_DBA_2

#define	TIM_DCR_DBA_3

#define	TIM_DCR_DBA_4

#define	TIM_DCR_DBL

#define	TIM_DCR_DBL_0

#define	TIM_DCR_DBL_1

#define	TIM_DCR_DBL_2

#define	TIM_DCR_DBL_3

#define	TIM_DCR_DBL_4

#define	TIM_DMAR_DMAB

#define	TIM_OR_TI4_RMP

#define	TIM_OR_TI4_RMP_0

#define	TIM_OR_TI4_RMP_1

#define	TIM_OR_ITR1_RMP

#define	TIM_OR_ITR1_RMP_0

#define	TIM_OR_ITR1_RMP_1

#define	USART_SR_PE

#define	USART_SR_FE

#define	USART_SR_NE

#define	USART_SR_ORE

#define	USART_SR_IDLE

#define	USART_SR_RXNE

#define	USART_SR_TC

#define	USART_SR_TXE

#define	USART_SR_LBD

#define	USART_SR_CTS

#define	USART_DR_DR

#define	USART_BRR_DIV_Fraction

#define	USART_BRR_DIV_Mantissa

#define	USART_CR1_SBK

#define	USART_CR1_RWU

#define	USART_CR1_RE

#define	USART_CR1_TE

#define	USART_CR1_IDLEIE

#define	USART_CR1_RXNEIE

#define	USART_CR1_TCIE

#define	USART_CR1_TXEIE

#define	USART_CR1_PEIE

#define	USART_CR1_PS

#define	USART_CR1_PCE

#define	USART_CR1_WAKE

#define	USART_CR1_M

#define	USART_CR1_UE

#define	USART_CR1_OVER8

#define	USART_CR2_ADD

#define	USART_CR2_LBDL

#define	USART_CR2_LBDIE

#define	USART_CR2_LBCL

#define	USART_CR2_CPHA

#define	USART_CR2_CPOL

#define	USART_CR2_CLKEN

#define	USART_CR2_STOP

#define	USART_CR2_STOP_0

#define	USART_CR2_STOP_1

#define	USART_CR2_LINEN

#define	USART_CR3_EIE

#define	USART_CR3_IREN

#define	USART_CR3_IRLP

#define	USART_CR3_HDSEL

#define	USART_CR3_NACK

#define	USART_CR3_SCEN

#define	USART_CR3_DMAR

#define	USART_CR3_DMAT

#define	USART_CR3_RTSE

#define	USART_CR3_CTSE

#define	USART_CR3_CTSIE

#define	USART_CR3_ONEBIT

#define	USART_GTPR_PSC

#define	USART_GTPR_PSC_0

#define	USART_GTPR_PSC_1

#define	USART_GTPR_PSC_2

#define	USART_GTPR_PSC_3

#define	USART_GTPR_PSC_4

#define	USART_GTPR_PSC_5

#define	USART_GTPR_PSC_6

#define	USART_GTPR_PSC_7

#define	USART_GTPR_GT

#define	WWDG_CR_T

#define	WWDG_CR_T0

#define	WWDG_CR_T1

#define	WWDG_CR_T2

#define	WWDG_CR_T3

#define	WWDG_CR_T4

#define	WWDG_CR_T5

#define	WWDG_CR_T6

#define	WWDG_CR_WDGA

#define	WWDG_CFR_W

#define	WWDG_CFR_W0

#define	WWDG_CFR_W1

#define	WWDG_CFR_W2

#define	WWDG_CFR_W3

#define	WWDG_CFR_W4

#define	WWDG_CFR_W5

#define	WWDG_CFR_W6

#define	WWDG_CFR_WDGTB

#define	WWDG_CFR_WDGTB0

#define	WWDG_CFR_WDGTB1

#define	WWDG_CFR_EWI

#define	WWDG_SR_EWIF

#define	DBGMCU_CR_TRACE_MODE_0

#define	DBGMCU_CR_TRACE_MODE_1

Typedefs
typedef enum IRQn	IRQn_Type
	STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_section.

typedef int32_t	s32

typedef const int32_t	sc32

typedef const int16_t	sc16

typedef const int8_t	sc8

typedef __I int32_t	vsc32

typedef __I int16_t	vsc16

typedef __I int8_t	vsc8

typedef const uint32_t	uc32

typedef const uint16_t	uc16

typedef const uint8_t	uc8

typedef __I uint32_t	vuc32

typedef __I uint16_t	vuc16

typedef __I uint8_t	vuc8

Enumerations
enum	IRQn { NonMaskableInt_IRQn, MemoryManagement_IRQn, BusFault_IRQn, UsageFault_IRQn, SVCall_IRQn, DebugMonitor_IRQn, PendSV_IRQn, SysTick_IRQn, WWDG_IRQn, PVD_IRQn, TAMP_STAMP_IRQn, RTC_WKUP_IRQn, FLASH_IRQn, RCC_IRQn, EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, EXTI4_IRQn, DMA1_Stream0_IRQn, DMA1_Stream1_IRQn, DMA1_Stream2_IRQn, DMA1_Stream3_IRQn, DMA1_Stream4_IRQn, DMA1_Stream5_IRQn, DMA1_Stream6_IRQn, ADC_IRQn, CAN1_TX_IRQn, CAN1_RX0_IRQn, CAN1_RX1_IRQn, CAN1_SCE_IRQn, EXTI9_5_IRQn, TIM1_BRK_TIM9_IRQn, TIM1_UP_TIM10_IRQn, TIM1_TRG_COM_TIM11_IRQn, TIM1_CC_IRQn, TIM2_IRQn, TIM3_IRQn, TIM4_IRQn, I2C1_EV_IRQn, I2C1_ER_IRQn, I2C2_EV_IRQn, I2C2_ER_IRQn, SPI1_IRQn, SPI2_IRQn, USART1_IRQn, USART2_IRQn, USART3_IRQn, EXTI15_10_IRQn, RTC_Alarm_IRQn, OTG_FS_WKUP_IRQn, TIM8_BRK_TIM12_IRQn, TIM8_UP_TIM13_IRQn, TIM8_TRG_COM_TIM14_IRQn, TIM8_CC_IRQn, DMA1_Stream7_IRQn, FSMC_IRQn, SDIO_IRQn, TIM5_IRQn, SPI3_IRQn, UART4_IRQn, UART5_IRQn, TIM6_DAC_IRQn, TIM7_IRQn, DMA2_Stream0_IRQn, DMA2_Stream1_IRQn, DMA2_Stream2_IRQn, DMA2_Stream3_IRQn, DMA2_Stream4_IRQn, ETH_IRQn, ETH_WKUP_IRQn, CAN2_TX_IRQn, CAN2_RX0_IRQn, CAN2_RX1_IRQn, CAN2_SCE_IRQn, OTG_FS_IRQn, DMA2_Stream5_IRQn, DMA2_Stream6_IRQn, DMA2_Stream7_IRQn, USART6_IRQn, I2C3_EV_IRQn, I2C3_ER_IRQn, OTG_HS_EP1_OUT_IRQn, OTG_HS_EP1_IN_IRQn, OTG_HS_WKUP_IRQn, OTG_HS_IRQn, DCMI_IRQn, CRYP_IRQn, HASH_RNG_IRQn, FPU_IRQn }
	STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_section. More...

Detailed Description

CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F4xx devices.

Author: MCD Application Team

Version: V1.0.0

Date

30-September-2011 The file is the unique include file that the application programmer is using in the C source code, usually in main.c. This file contains:

Configuration section that allows to select:
- The device used in the target application
- To use or not the peripheral�s drivers in application code(i.e. code will be based on direct access to peripheral�s registers rather than drivers API), this option is controlled by "#define USE_STDPERIPH_DRIVER"
- To change few application-specific parameters such as the HSE crystal frequency
Data structures and the address mapping for all peripherals
Peripheral's registers declarations and bits definition
Macros to access peripheral�s registers hardware

Attention

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

Definition in file stm32f4xx.h.

Data Structures

Macros

Typedefs

Enumerations

Detailed Description

© COPYRIGHT 2011 STMicroelectronics