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ARMEBS4
revision-26.06.2015
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DCMI. More...
#include "C:/Programs/ARMEBS4/current/doc/eclipse-doc/ext/libheivs_stm32/include/stm32/stm32f4xx.h"
Data Fields | |
__IO uint32_t | CR |
__IO uint32_t | SR |
__IO uint32_t | RISR |
__IO uint32_t | IER |
__IO uint32_t | MISR |
__IO uint32_t | ICR |
__IO uint32_t | ESCR |
__IO uint32_t | ESUR |
__IO uint32_t | CWSTRTR |
__IO uint32_t | CWSIZER |
__IO uint32_t | DR |
DCMI.
Definition at line 441 of file stm32f4xx.h.
__IO uint32_t DCMI_TypeDef::CR |
DCMI control register 1, Address offset: 0x00
Definition at line 443 of file stm32f4xx.h.
__IO uint32_t DCMI_TypeDef::SR |
DCMI status register, Address offset: 0x04
Definition at line 444 of file stm32f4xx.h.
__IO uint32_t DCMI_TypeDef::RISR |
DCMI raw interrupt status register, Address offset: 0x08
Definition at line 445 of file stm32f4xx.h.
__IO uint32_t DCMI_TypeDef::IER |
DCMI interrupt enable register, Address offset: 0x0C
Definition at line 446 of file stm32f4xx.h.
__IO uint32_t DCMI_TypeDef::MISR |
DCMI masked interrupt status register, Address offset: 0x10
Definition at line 447 of file stm32f4xx.h.
__IO uint32_t DCMI_TypeDef::ICR |
DCMI interrupt clear register, Address offset: 0x14
Definition at line 448 of file stm32f4xx.h.
__IO uint32_t DCMI_TypeDef::ESCR |
DCMI embedded synchronization code register, Address offset: 0x18
Definition at line 449 of file stm32f4xx.h.
__IO uint32_t DCMI_TypeDef::ESUR |
DCMI embedded synchronization unmask register, Address offset: 0x1C
Definition at line 450 of file stm32f4xx.h.
__IO uint32_t DCMI_TypeDef::CWSTRTR |
DCMI crop window start, Address offset: 0x20
Definition at line 451 of file stm32f4xx.h.
__IO uint32_t DCMI_TypeDef::CWSIZER |
DCMI crop window size, Address offset: 0x24
Definition at line 452 of file stm32f4xx.h.
__IO uint32_t DCMI_TypeDef::DR |
DCMI data register, Address offset: 0x28
Definition at line 453 of file stm32f4xx.h.