ARMEBS4  revision-26.06.2015
stm32f4xx.h
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1 /**
2  ******************************************************************************
3  * @file stm32f4xx.h
4  * @author MCD Application Team
5  * @version V1.0.0
6  * @date 30-September-2011
7  * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
8  * This file contains all the peripheral register's definitions, bits
9  * definitions and memory mapping for STM32F4xx devices.
10  *
11  * The file is the unique include file that the application programmer
12  * is using in the C source code, usually in main.c. This file contains:
13  * - Configuration section that allows to select:
14  * - The device used in the target application
15  * - To use or not the peripheral�s drivers in application code(i.e.
16  * code will be based on direct access to peripheral�s registers
17  * rather than drivers API), this option is controlled by
18  * "#define USE_STDPERIPH_DRIVER"
19  * - To change few application-specific parameters such as the HSE
20  * crystal frequency
21  * - Data structures and the address mapping for all peripherals
22  * - Peripheral's registers declarations and bits definition
23  * - Macros to access peripheral�s registers hardware
24  *
25  ******************************************************************************
26  * @attention
27  *
28  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
29  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
30  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
31  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
32  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
33  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
34  *
35  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
36  ******************************************************************************
37  */
38 
39 /** @addtogroup CMSIS
40  * @{
41  */
42 
43 /** @addtogroup stm32f4xx
44  * @{
45  */
46 
47 #ifndef __STM32F4xx_H
48 #define __STM32F4xx_H
49 
50 #ifdef __cplusplus
51  extern "C" {
52 #endif /* __cplusplus */
53 
54 /** @addtogroup Library_configuration_section
55  * @{
56  */
57 
58 /* Uncomment the line below according to the target STM32 device used in your
59  application
60  */
61 
62 #if !defined (STM32F4XX)
63  #define STM32F4XX
64 #endif
65 
66 /* Tip: To avoid modifying this file each time you need to switch between these
67  devices, you can define the device in your toolchain compiler preprocessor.
68  */
69 
70 #if !defined (STM32F4XX)
71  #error "Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)"
72 #endif
73 
74 #if !defined (USE_STDPERIPH_DRIVER)
75 /**
76  * @brief Comment the line below if you will not use the peripherals drivers.
77  In this case, these drivers will not be included and the application code will
78  be based on direct access to peripherals registers
79  */
80  /*#define USE_STDPERIPH_DRIVER*/
81 #endif /* USE_STDPERIPH_DRIVER */
82 
83 /**
84  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
85  Timeout value
86  */
87 #if !defined (HSE_STARTUP_TIMEOUT)
88  #define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
89 #endif /* HSE_STARTUP_TIMEOUT */
90 
91 #if !defined (HSI_VALUE)
92  #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
93 #endif /* HSI_VALUE */
94 
95 /**
96  * @brief STM32F4XX Standard Peripherals Library version number V1.0.0
97  */
98 #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
99 #define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
100 #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
101 #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
102 #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
103  |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
104  |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
105  |(__STM32F4XX_STDPERIPH_VERSION_RC))
106 
107 /**
108  * @}
109  */
110 
111 /** @addtogroup Configuration_section_for_CMSIS
112  * @{
113  */
114 
115 /**
116  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
117  */
118 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
119 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
120 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
121 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
122 
123 /**
124  * @brief STM32F4XX Interrupt Number Definition, according to the selected device
125  * in @ref Library_configuration_section
126  */
127 typedef enum IRQn
128 {
129 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
130  NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
131  MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
132  BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
133  UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
134  SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
135  DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
136  PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
137  SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
138 /****** STM32 specific Interrupt Numbers **********************************************************************/
139  WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
140  PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
141  TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
142  RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
143  FLASH_IRQn = 4, /*!< FLASH global Interrupt */
144  RCC_IRQn = 5, /*!< RCC global Interrupt */
145  EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
146  EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
147  EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
148  EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
149  EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
150  DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
151  DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
152  DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
153  DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
154  DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
155  DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
156  DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
157  ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
158  CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
159  CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
160  CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
161  CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
162  EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
163  TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
164  TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
165  TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
166  TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
167  TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
168  TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
169  TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
170  I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
171  I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
172  I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
173  I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
174  SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
175  SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
176  USART1_IRQn = 37, /*!< USART1 global Interrupt */
177  USART2_IRQn = 38, /*!< USART2 global Interrupt */
178  USART3_IRQn = 39, /*!< USART3 global Interrupt */
179  EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
180  RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
181  OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
182  TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
183  TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
184  TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
185  TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
186  DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
187  FSMC_IRQn = 48, /*!< FSMC global Interrupt */
188  SDIO_IRQn = 49, /*!< SDIO global Interrupt */
189  TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
190  SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
191  UART4_IRQn = 52, /*!< UART4 global Interrupt */
192  UART5_IRQn = 53, /*!< UART5 global Interrupt */
193  TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
194  TIM7_IRQn = 55, /*!< TIM7 global interrupt */
195  DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
196  DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
197  DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
198  DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
199  DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
200  ETH_IRQn = 61, /*!< Ethernet global Interrupt */
201  ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
202  CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
203  CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
204  CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
205  CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
206  OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
207  DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
208  DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
209  DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
210  USART6_IRQn = 71, /*!< USART6 global interrupt */
211  I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
212  I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
213  OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
214  OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
215  OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
216  OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
217  DCMI_IRQn = 78, /*!< DCMI global interrupt */
218  CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
219  HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
220  FPU_IRQn = 81 /*!< FPU global interrupt */
221 } IRQn_Type;
222 
223 /**
224  * @}
225  */
226 
227 #if defined (ARM_MATH_CM4) || defined (__ARM_ARCH_7EM__)
228  #if !defined(__SOFTFP__)
229  #define __FPU_PRESENT 1
230  #endif
231 #else
232 #error set your compiler flags for cortex-m4
233 #endif
234 #include "cmsis/core_cm4.h"
235 #include "stm32/system_stm32f4xx.h"
236 #include <stdint.h>
237 
238 /** @addtogroup Exported_types
239  * @{
240  */
241 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
242 typedef int32_t s32;
243 typedef int16_t s16;
244 typedef int8_t s8;
245 
246 typedef const int32_t sc32; /*!< Read Only */
247 typedef const int16_t sc16; /*!< Read Only */
248 typedef const int8_t sc8; /*!< Read Only */
249 
250 typedef __IO int32_t vs32;
251 typedef __IO int16_t vs16;
252 typedef __IO int8_t vs8;
253 
254 typedef __I int32_t vsc32; /*!< Read Only */
255 typedef __I int16_t vsc16; /*!< Read Only */
256 typedef __I int8_t vsc8; /*!< Read Only */
257 
258 typedef uint32_t u32;
259 typedef uint16_t u16;
260 typedef uint8_t u8;
261 
262 typedef const uint32_t uc32; /*!< Read Only */
263 typedef const uint16_t uc16; /*!< Read Only */
264 typedef const uint8_t uc8; /*!< Read Only */
265 
266 typedef __IO uint32_t vu32;
267 typedef __IO uint16_t vu16;
268 typedef __IO uint8_t vu8;
269 
270 typedef __I uint32_t vuc32; /*!< Read Only */
271 typedef __I uint16_t vuc16; /*!< Read Only */
272 typedef __I uint8_t vuc8; /*!< Read Only */
273 
274 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
275 
276 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
277 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
278 
279 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
280 
281 /**
282  * @}
283  */
284 
285 /** @addtogroup Peripheral_registers_structures
286  * @{
287  */
288 
289 /**
290  * @brief Analog to Digital Converter
291  */
292 
293 typedef struct
294 {
295  __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
296  __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
297  __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
298  __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
299  __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
300  __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
301  __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
302  __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
303  __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
304  __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
305  __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
306  __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
307  __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
308  __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
309  __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
310  __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
311  __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
312  __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
313  __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
314  __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
315 } ADC_TypeDef;
316 
317 typedef struct
318 {
319  __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
320  __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
321  __IO uint32_t CDR; /*!< ADC common regular data register for dual
322  AND triple modes, Address offset: ADC1 base address + 0x308 */
323 } ADC_Common_TypeDef;
324 
325 
326 /**
327  * @brief Controller Area Network TxMailBox
328  */
329 
330 typedef struct
331 {
332  __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
333  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
334  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
335  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
336 } CAN_TxMailBox_TypeDef;
337 
338 /**
339  * @brief Controller Area Network FIFOMailBox
340  */
341 
342 typedef struct
343 {
344  __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
345  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
346  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
347  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
348 } CAN_FIFOMailBox_TypeDef;
349 
350 /**
351  * @brief Controller Area Network FilterRegister
352  */
353 
354 typedef struct
355 {
356  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
357  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
358 } CAN_FilterRegister_TypeDef;
359 
360 /**
361  * @brief Controller Area Network
362  */
363 
364 typedef struct
365 {
366  __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
367  __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
368  __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
369  __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
370  __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
371  __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
372  __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
373  __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
374  uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
375  CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
376  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
377  uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
378  __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
379  __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
380  uint32_t RESERVED2; /*!< Reserved, 0x208 */
381  __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
382  uint32_t RESERVED3; /*!< Reserved, 0x210 */
383  __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
384  uint32_t RESERVED4; /*!< Reserved, 0x218 */
385  __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
386  uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
387  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
388 } CAN_TypeDef;
389 
390 /**
391  * @brief CRC calculation unit
392  */
393 
394 typedef struct
395 {
396  __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
397  __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
398  uint8_t RESERVED0; /*!< Reserved, 0x05 */
399  uint16_t RESERVED1; /*!< Reserved, 0x06 */
400  __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
401 } CRC_TypeDef;
402 
403 /**
404  * @brief Digital to Analog Converter
405  */
406 
407 typedef struct
408 {
409  __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
410  __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
411  __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
412  __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
413  __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
414  __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
415  __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
416  __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
417  __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
418  __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
419  __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
420  __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
421  __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
422  __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
423 } DAC_TypeDef;
424 
425 /**
426  * @brief Debug MCU
427  */
428 
429 typedef struct
430 {
431  __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
432  __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
433  __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
434  __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
435 }DBGMCU_TypeDef;
436 
437 /**
438  * @brief DCMI
439  */
440 
441 typedef struct
442 {
443  __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
444  __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
445  __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
446  __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
447  __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
448  __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
449  __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
450  __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
451  __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
452  __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
453  __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
454 } DCMI_TypeDef;
455 
456 /**
457  * @brief DMA Controller
458  */
459 
460 typedef struct
461 {
462  __IO uint32_t CR; /*!< DMA stream x configuration register */
463  __IO uint32_t NDTR; /*!< DMA stream x number of data register */
464  __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
465  __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
466  __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
467  __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
468 } DMA_Stream_TypeDef;
469 
470 typedef struct
471 {
472  __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
473  __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
474  __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
475  __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
476 } DMA_TypeDef;
477 
478 /**
479  * @brief Ethernet MAC
480  */
481 
482 typedef struct
483 {
484  __IO uint32_t MACCR;
485  __IO uint32_t MACFFR;
486  __IO uint32_t MACHTHR;
487  __IO uint32_t MACHTLR;
488  __IO uint32_t MACMIIAR;
489  __IO uint32_t MACMIIDR;
490  __IO uint32_t MACFCR;
491  __IO uint32_t MACVLANTR; /* 8 */
492  uint32_t RESERVED0[2];
493  __IO uint32_t MACRWUFFR; /* 11 */
494  __IO uint32_t MACPMTCSR;
495  uint32_t RESERVED1[2];
496  __IO uint32_t MACSR; /* 15 */
497  __IO uint32_t MACIMR;
498  __IO uint32_t MACA0HR;
499  __IO uint32_t MACA0LR;
500  __IO uint32_t MACA1HR;
501  __IO uint32_t MACA1LR;
502  __IO uint32_t MACA2HR;
503  __IO uint32_t MACA2LR;
504  __IO uint32_t MACA3HR;
505  __IO uint32_t MACA3LR; /* 24 */
506  uint32_t RESERVED2[40];
507  __IO uint32_t MMCCR; /* 65 */
508  __IO uint32_t MMCRIR;
509  __IO uint32_t MMCTIR;
510  __IO uint32_t MMCRIMR;
511  __IO uint32_t MMCTIMR; /* 69 */
512  uint32_t RESERVED3[14];
513  __IO uint32_t MMCTGFSCCR; /* 84 */
514  __IO uint32_t MMCTGFMSCCR;
515  uint32_t RESERVED4[5];
516  __IO uint32_t MMCTGFCR;
517  uint32_t RESERVED5[10];
518  __IO uint32_t MMCRFCECR;
519  __IO uint32_t MMCRFAECR;
520  uint32_t RESERVED6[10];
521  __IO uint32_t MMCRGUFCR;
522  uint32_t RESERVED7[334];
523  __IO uint32_t PTPTSCR;
524  __IO uint32_t PTPSSIR;
525  __IO uint32_t PTPTSHR;
526  __IO uint32_t PTPTSLR;
527  __IO uint32_t PTPTSHUR;
528  __IO uint32_t PTPTSLUR;
529  __IO uint32_t PTPTSAR;
530  __IO uint32_t PTPTTHR;
531  __IO uint32_t PTPTTLR;
532  __IO uint32_t RESERVED8;
533  __IO uint32_t PTPTSSR;
534  uint32_t RESERVED9[565];
535  __IO uint32_t DMABMR;
536  __IO uint32_t DMATPDR;
537  __IO uint32_t DMARPDR;
538  __IO uint32_t DMARDLAR;
539  __IO uint32_t DMATDLAR;
540  __IO uint32_t DMASR;
541  __IO uint32_t DMAOMR;
542  __IO uint32_t DMAIER;
543  __IO uint32_t DMAMFBOCR;
544  __IO uint32_t DMARSWTR;
545  uint32_t RESERVED10[8];
546  __IO uint32_t DMACHTDR;
547  __IO uint32_t DMACHRDR;
548  __IO uint32_t DMACHTBAR;
549  __IO uint32_t DMACHRBAR;
550 } ETH_TypeDef;
551 
552 /**
553  * @brief External Interrupt/Event Controller
554  */
555 
556 typedef struct
557 {
558  __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
559  __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
560  __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
561  __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
562  __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
563  __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
564 } EXTI_TypeDef;
565 
566 /**
567  * @brief FLASH Registers
568  */
569 
570 typedef struct
571 {
572  __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
573  __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
574  __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
575  __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
576  __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
577  __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */
578 } FLASH_TypeDef;
579 
580 /**
581  * @brief Flexible Static Memory Controller
582  */
583 
584 typedef struct
585 {
586  __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
587 } FSMC_Bank1_TypeDef;
588 
589 /**
590  * @brief Flexible Static Memory Controller Bank1E
591  */
592 
593 typedef struct
594 {
595  __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
596 } FSMC_Bank1E_TypeDef;
597 
598 /**
599  * @brief Flexible Static Memory Controller Bank2
600  */
601 
602 typedef struct
603 {
604  __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
605  __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
606  __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
607  __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
608  uint32_t RESERVED0; /*!< Reserved, 0x70 */
609  __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
610 } FSMC_Bank2_TypeDef;
611 
612 /**
613  * @brief Flexible Static Memory Controller Bank3
614  */
615 
616 typedef struct
617 {
618  __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
619  __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
620  __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
621  __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
622  uint32_t RESERVED0; /*!< Reserved, 0x90 */
623  __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
624 } FSMC_Bank3_TypeDef;
625 
626 /**
627  * @brief Flexible Static Memory Controller Bank4
628  */
629 
630 typedef struct
631 {
632  __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
633  __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
634  __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
635  __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
636  __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
637 } FSMC_Bank4_TypeDef;
638 
639 /**
640  * @brief General Purpose I/O
641  */
642 
643 typedef struct
644 {
645  __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
646  __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
647  __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
648  __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
649  __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
650  __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
651  __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
652  __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
653  __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
654  __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
655 } GPIO_TypeDef;
656 
657 /**
658  * @brief System configuration controller
659  */
660 
661 typedef struct
662 {
663  __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
664  __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
665  __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
666  uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
667  __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
668 } SYSCFG_TypeDef;
669 
670 /**
671  * @brief Inter-integrated Circuit Interface
672  */
673 
674 typedef struct
675 {
676  __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
677  uint16_t RESERVED0; /*!< Reserved, 0x02 */
678  __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
679  uint16_t RESERVED1; /*!< Reserved, 0x06 */
680  __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
681  uint16_t RESERVED2; /*!< Reserved, 0x0A */
682  __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
683  uint16_t RESERVED3; /*!< Reserved, 0x0E */
684  __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
685  uint16_t RESERVED4; /*!< Reserved, 0x12 */
686  __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
687  uint16_t RESERVED5; /*!< Reserved, 0x16 */
688  __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
689  uint16_t RESERVED6; /*!< Reserved, 0x1A */
690  __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
691  uint16_t RESERVED7; /*!< Reserved, 0x1E */
692  __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
693  uint16_t RESERVED8; /*!< Reserved, 0x22 */
694 } I2C_TypeDef;
695 
696 /**
697  * @brief Independent WATCHDOG
698  */
699 
700 typedef struct
701 {
702  __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
703  __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
704  __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
705  __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
706 } IWDG_TypeDef;
707 
708 /**
709  * @brief Power Control
710  */
711 
712 typedef struct
713 {
714  __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
715  __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
716 } PWR_TypeDef;
717 
718 /**
719  * @brief Reset and Clock Control
720  */
721 
722 typedef struct
723 {
724  __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
725  __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
726  __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
727  __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
728  __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
729  __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
730  __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
731  uint32_t RESERVED0; /*!< Reserved, 0x1C */
732  __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
733  __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
734  uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
735  __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
736  __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
737  __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
738  uint32_t RESERVED2; /*!< Reserved, 0x3C */
739  __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
740  __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
741  uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
742  __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
743  __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
744  __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
745  uint32_t RESERVED4; /*!< Reserved, 0x5C */
746  __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
747  __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
748  uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
749  __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
750  __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
751  uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
752  __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
753  __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
754 } RCC_TypeDef;
755 
756 /**
757  * @brief Real-Time Clock
758  */
759 
760 typedef struct
761 {
762  __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
763  __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
764  __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
765  __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
766  __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
767  __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
768  __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
769  __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
770  __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
771  __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
772  __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
773  __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
774  __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
775  __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
776  __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
777  __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
778  __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
779  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
780  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
781  uint32_t RESERVED7; /*!< Reserved, 0x4C */
782  __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
783  __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
784  __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
785  __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
786  __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
787  __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
788  __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
789  __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
790  __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
791  __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
792  __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
793  __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
794  __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
795  __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
796  __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
797  __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
798  __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
799  __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
800  __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
801  __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
802 } RTC_TypeDef;
803 
804 /**
805  * @brief SD host Interface
806  */
807 
808 typedef struct
809 {
810  __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
811  __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
812  __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
813  __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
814  __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
815  __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
816  __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
817  __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
818  __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
819  __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
820  __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
821  __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
822  __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
823  __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
824  __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
825  __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
826  uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
827  __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
828  uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
829  __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
830 } SDIO_TypeDef;
831 
832 /**
833  * @brief Serial Peripheral Interface
834  */
835 
836 typedef struct
837 {
838  __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
839  uint16_t RESERVED0; /*!< Reserved, 0x02 */
840  __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
841  uint16_t RESERVED1; /*!< Reserved, 0x06 */
842  __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
843  uint16_t RESERVED2; /*!< Reserved, 0x0A */
844  __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
845  uint16_t RESERVED3; /*!< Reserved, 0x0E */
846  __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
847  uint16_t RESERVED4; /*!< Reserved, 0x12 */
848  __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
849  uint16_t RESERVED5; /*!< Reserved, 0x16 */
850  __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
851  uint16_t RESERVED6; /*!< Reserved, 0x1A */
852  __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
853  uint16_t RESERVED7; /*!< Reserved, 0x1E */
854  __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
855  uint16_t RESERVED8; /*!< Reserved, 0x22 */
856 } SPI_TypeDef;
857 
858 /**
859  * @brief TIM
860  */
861 
862 typedef struct
863 {
864  __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
865  uint16_t RESERVED0; /*!< Reserved, 0x02 */
866  __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
867  uint16_t RESERVED1; /*!< Reserved, 0x06 */
868  __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
869  uint16_t RESERVED2; /*!< Reserved, 0x0A */
870  __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
871  uint16_t RESERVED3; /*!< Reserved, 0x0E */
872  __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
873  uint16_t RESERVED4; /*!< Reserved, 0x12 */
874  __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
875  uint16_t RESERVED5; /*!< Reserved, 0x16 */
876  __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
877  uint16_t RESERVED6; /*!< Reserved, 0x1A */
878  __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
879  uint16_t RESERVED7; /*!< Reserved, 0x1E */
880  __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
881  uint16_t RESERVED8; /*!< Reserved, 0x22 */
882  __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
883  __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
884  uint16_t RESERVED9; /*!< Reserved, 0x2A */
885  __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
886  __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
887  uint16_t RESERVED10; /*!< Reserved, 0x32 */
888  __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
889  __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
890  __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
891  __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
892  __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
893  uint16_t RESERVED11; /*!< Reserved, 0x46 */
894  __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
895  uint16_t RESERVED12; /*!< Reserved, 0x4A */
896  __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
897  uint16_t RESERVED13; /*!< Reserved, 0x4E */
898  __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
899  uint16_t RESERVED14; /*!< Reserved, 0x52 */
900 } TIM_TypeDef;
901 
902 /**
903  * @brief Universal Synchronous Asynchronous Receiver Transmitter
904  */
905 
906 typedef struct
907 {
908  __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
909  uint16_t RESERVED0; /*!< Reserved, 0x02 */
910  __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
911  uint16_t RESERVED1; /*!< Reserved, 0x06 */
912  __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
913  uint16_t RESERVED2; /*!< Reserved, 0x0A */
914  __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
915  uint16_t RESERVED3; /*!< Reserved, 0x0E */
916  __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
917  uint16_t RESERVED4; /*!< Reserved, 0x12 */
918  __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
919  uint16_t RESERVED5; /*!< Reserved, 0x16 */
920  __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
921  uint16_t RESERVED6; /*!< Reserved, 0x1A */
922 } USART_TypeDef;
923 
924 /**
925  * @brief Window WATCHDOG
926  */
927 
928 typedef struct
929 {
930  __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
931  __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
932  __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
933 } WWDG_TypeDef;
934 
935 /**
936  * @brief Crypto Processor
937  */
938 
939 typedef struct
940 {
941  __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
942  __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
943  __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
944  __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
945  __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
946  __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
947  __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
948  __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
949  __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
950  __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
951  __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
952  __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
953  __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
954  __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
955  __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
956  __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
957  __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
958  __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
959  __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
960  __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
961 } CRYP_TypeDef;
962 
963 /**
964  * @brief HASH
965  */
966 
967 typedef struct
968 {
969  __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
970  __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
971  __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
972  __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
973  __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
974  __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
975  uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
976  __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */
977 } HASH_TypeDef;
978 
979 /**
980  * @brief HASH
981  */
982 
983 typedef struct
984 {
985  __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
986  __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
987  __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
988 } RNG_TypeDef;
989 
990 /**
991  * @}
992  */
993 
994 /** @addtogroup Peripheral_memory_map
995  * @{
996  */
997 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
998 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
999 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
1000 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
1001 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
1002 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
1003 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
1004 
1005 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
1006 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
1007 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
1008 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
1009 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
1010 
1011 /* Legacy defines */
1012 #define SRAM_BASE SRAM1_BASE
1013 #define SRAM_BB_BASE SRAM1_BB_BASE
1014 
1015 
1016 /*!< Peripheral memory map */
1017 #define APB1PERIPH_BASE PERIPH_BASE
1018 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
1019 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
1020 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
1021 
1022 /*!< APB1 peripherals */
1023 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
1024 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
1025 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
1026 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
1027 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
1028 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
1029 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
1030 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
1031 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
1032 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
1033 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
1034 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
1035 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
1036 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
1037 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
1038 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
1039 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
1040 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
1041 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
1042 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
1043 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
1044 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
1045 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
1046 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
1047 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
1048 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
1049 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
1050 
1051 /*!< APB2 peripherals */
1052 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
1053 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
1054 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
1055 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
1056 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
1057 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
1058 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
1059 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
1060 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
1061 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
1062 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
1063 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
1064 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
1065 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
1066 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
1067 
1068 /*!< AHB1 peripherals */
1069 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
1070 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
1071 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
1072 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
1073 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
1074 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
1075 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
1076 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
1077 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
1078 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
1079 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
1080 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
1081 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
1082 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
1083 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
1084 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
1085 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
1086 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
1087 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
1088 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
1089 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
1090 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
1091 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
1092 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
1093 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
1094 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
1095 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
1096 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
1097 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
1098 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
1099 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
1100 #define ETH_MAC_BASE (ETH_BASE)
1101 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
1102 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
1103 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
1104 
1105 /*!< AHB2 peripherals */
1106 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
1107 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
1108 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
1109 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
1110 
1111 /*!< FSMC Bankx registers base address */
1112 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
1113 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
1114 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
1115 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
1116 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
1117 
1118 /* Debug MCU registers base address */
1119 #define DBGMCU_BASE ((uint32_t )0xE0042000)
1120 
1121 /**
1122  * @}
1123  */
1124 
1125 /** @addtogroup Peripheral_declaration
1126  * @{
1127  */
1128 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1129 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1130 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1131 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1132 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1133 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1134 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1135 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1136 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1137 #define RTC ((RTC_TypeDef *) RTC_BASE)
1138 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1139 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1140 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1141 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1142 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1143 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1144 #define USART2 ((USART_TypeDef *) USART2_BASE)
1145 #define USART3 ((USART_TypeDef *) USART3_BASE)
1146 #define UART4 ((USART_TypeDef *) UART4_BASE)
1147 #define UART5 ((USART_TypeDef *) UART5_BASE)
1148 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1149 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1150 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1151 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1152 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1153 #define PWR ((PWR_TypeDef *) PWR_BASE)
1154 #define DAC ((DAC_TypeDef *) DAC_BASE)
1155 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1156 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1157 #define USART1 ((USART_TypeDef *) USART1_BASE)
1158 #define USART6 ((USART_TypeDef *) USART6_BASE)
1159 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1160 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1161 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1162 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1163 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1164 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1165 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1166 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1167 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1168 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1169 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1170 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1171 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1172 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1173 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1174 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1175 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1176 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1177 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1178 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1179 #define CRC ((CRC_TypeDef *) CRC_BASE)
1180 #define RCC ((RCC_TypeDef *) RCC_BASE)
1181 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1182 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1183 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1184 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1185 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1186 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1187 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1188 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1189 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1190 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1191 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1192 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1193 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1194 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1195 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1196 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1197 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1198 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1199 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1200 #define ETH ((ETH_TypeDef *) ETH_BASE)
1201 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1202 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1203 #define HASH ((HASH_TypeDef *) HASH_BASE)
1204 #define RNG ((RNG_TypeDef *) RNG_BASE)
1205 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1206 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1207 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
1208 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
1209 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1210 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1211 
1212 /**
1213  * @}
1214  */
1215 
1216 /** @addtogroup Exported_constants
1217  * @{
1218  */
1219 
1220  /** @addtogroup Peripheral_Registers_Bits_Definition
1221  * @{
1222  */
1223 
1224 /******************************************************************************/
1225 /* Peripheral Registers_Bits_Definition */
1226 /******************************************************************************/
1227 
1228 /******************************************************************************/
1229 /* */
1230 /* Analog to Digital Converter */
1231 /* */
1232 /******************************************************************************/
1233 /******************** Bit definition for ADC_SR register ********************/
1234 #define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
1235 #define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
1236 #define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
1237 #define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
1238 #define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
1239 #define ADC_SR_OVR ((uint8_t)0x20) /*!<Overrun flag */
1240 
1241 /******************* Bit definition for ADC_CR1 register ********************/
1242 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1243 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1244 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1245 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1246 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1247 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1248 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
1249 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
1250 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
1251 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
1252 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
1253 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
1254 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
1255 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
1256 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1257 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
1258 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
1259 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
1260 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
1261 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
1262 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
1263 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1264 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1265 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
1266 
1267 /******************* Bit definition for ADC_CR2 register ********************/
1268 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
1269 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
1270 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
1271 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
1272 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
1273 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
1274 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1275 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1276 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1277 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
1278 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
1279 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1280 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1281 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1282 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
1283 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1284 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1285 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1286 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1287 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
1288 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1289 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
1290 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
1291 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
1292 
1293 /****************** Bit definition for ADC_SMPR1 register *******************/
1294 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1295 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1296 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1297 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1298 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1299 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1300 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1301 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1302 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1303 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1304 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1305 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1306 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1307 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1308 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1309 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1310 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1311 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1312 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1313 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1314 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1315 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1316 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1317 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1318 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1319 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1320 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1321 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1322 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1323 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1324 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1325 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1326 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1327 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1328 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1329 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1330 
1331 /****************** Bit definition for ADC_SMPR2 register *******************/
1332 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1333 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1334 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1335 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1336 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1337 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1338 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1339 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1340 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1341 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1342 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1343 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1344 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1345 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1346 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1347 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1348 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1349 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1350 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1351 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1352 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1353 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1354 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1355 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1356 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1357 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1358 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1359 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1360 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1361 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1362 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1363 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1364 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1365 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1366 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1367 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1368 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1369 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
1370 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
1371 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
1372 
1373 /****************** Bit definition for ADC_JOFR1 register *******************/
1374 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
1375 
1376 /****************** Bit definition for ADC_JOFR2 register *******************/
1377 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
1378 
1379 /****************** Bit definition for ADC_JOFR3 register *******************/
1380 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
1381 
1382 /****************** Bit definition for ADC_JOFR4 register *******************/
1383 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
1384 
1385 /******************* Bit definition for ADC_HTR register ********************/
1386 #define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
1387 
1388 /******************* Bit definition for ADC_LTR register ********************/
1389 #define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
1390 
1391 /******************* Bit definition for ADC_SQR1 register *******************/
1392 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1393 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1394 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1395 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1396 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1397 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1398 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1399 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1400 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1401 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1402 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1403 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1404 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1405 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1406 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1407 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1408 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1409 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1410 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1411 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1412 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1413 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1414 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1415 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1416 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
1417 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1418 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1419 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1420 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1421 
1422 /******************* Bit definition for ADC_SQR2 register *******************/
1423 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1424 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1425 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1426 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1427 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1428 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1429 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1430 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1431 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1432 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1433 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1434 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1435 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1436 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1437 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1438 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1439 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1440 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1441 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1442 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1443 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1444 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1445 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1446 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1447 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1448 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1449 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1450 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1451 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1452 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1453 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1454 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1455 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1456 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1457 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1458 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1459 
1460 /******************* Bit definition for ADC_SQR3 register *******************/
1461 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1462 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1463 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1464 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1465 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1466 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1467 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1468 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1469 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1470 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1471 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1472 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1473 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1474 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1475 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1476 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1477 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1478 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1479 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1480 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1481 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1482 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1483 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1484 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1485 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1486 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1487 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1488 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1489 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1490 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1491 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1492 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1493 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1494 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1495 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1496 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1497 
1498 /******************* Bit definition for ADC_JSQR register *******************/
1499 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1500 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1501 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1502 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1503 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1504 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1505 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1506 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1507 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1508 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1509 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1510 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1511 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1512 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1513 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1514 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1515 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1516 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1517 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1518 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1519 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1520 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1521 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1522 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1523 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
1524 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1525 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1526 
1527 /******************* Bit definition for ADC_JDR1 register *******************/
1528 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1529 
1530 /******************* Bit definition for ADC_JDR2 register *******************/
1531 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1532 
1533 /******************* Bit definition for ADC_JDR3 register *******************/
1534 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1535 
1536 /******************* Bit definition for ADC_JDR4 register *******************/
1537 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1538 
1539 /******************** Bit definition for ADC_DR register ********************/
1540 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
1541 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
1542 
1543 /******************* Bit definition for ADC_CSR register ********************/
1544 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
1545 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
1546 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
1547 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
1548 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
1549 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
1550 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
1551 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
1552 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
1553 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
1554 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
1555 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
1556 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
1557 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
1558 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
1559 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
1560 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
1561 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
1562 
1563 /******************* Bit definition for ADC_CCR register ********************/
1564 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1565 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1566 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1567 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1568 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1569 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1570 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1571 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
1572 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
1573 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
1574 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
1575 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
1576 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1577 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
1578 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
1579 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
1580 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1581 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1582 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
1583 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
1584 
1585 /******************* Bit definition for ADC_CDR register ********************/
1586 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
1587 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
1588 
1589 /******************************************************************************/
1590 /* */
1591 /* Controller Area Network */
1592 /* */
1593 /******************************************************************************/
1594 /*!<CAN control and status registers */
1595 /******************* Bit definition for CAN_MCR register ********************/
1596 #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
1597 #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
1598 #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
1599 #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
1600 #define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
1601 #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
1602 #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
1603 #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
1604 #define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
1605 
1606 /******************* Bit definition for CAN_MSR register ********************/
1607 #define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
1608 #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
1609 #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
1610 #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
1611 #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
1612 #define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
1613 #define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
1614 #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
1615 #define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
1616 
1617 /******************* Bit definition for CAN_TSR register ********************/
1618 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
1619 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
1620 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
1621 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
1622 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
1623 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
1624 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
1625 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
1626 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
1627 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
1628 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
1629 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
1630 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
1631 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
1632 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
1633 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
1634 
1635 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
1636 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
1637 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
1638 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
1639 
1640 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
1641 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
1642 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
1643 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
1644 
1645 /******************* Bit definition for CAN_RF0R register *******************/
1646 #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
1647 #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
1648 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
1649 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
1650 
1651 /******************* Bit definition for CAN_RF1R register *******************/
1652 #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
1653 #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
1654 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
1655 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
1656 
1657 /******************** Bit definition for CAN_IER register *******************/
1658 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
1659 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
1660 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
1661 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
1662 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
1663 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
1664 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
1665 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
1666 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
1667 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
1668 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
1669 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
1670 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
1671 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
1672 
1673 /******************** Bit definition for CAN_ESR register *******************/
1674 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
1675 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
1676 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
1677 
1678 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
1679 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
1680 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
1681 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
1682 
1683 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
1684 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
1685 
1686 /******************* Bit definition for CAN_BTR register ********************/
1687 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
1688 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
1689 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
1690 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
1691 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
1692 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
1693 
1694 /*!<Mailbox registers */
1695 /****************** Bit definition for CAN_TI0R register ********************/
1696 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1697 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1698 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1699 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1700 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1701 
1702 /****************** Bit definition for CAN_TDT0R register *******************/
1703 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1704 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1705 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1706 
1707 /****************** Bit definition for CAN_TDL0R register *******************/
1708 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1709 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1710 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1711 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1712 
1713 /****************** Bit definition for CAN_TDH0R register *******************/
1714 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1715 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1716 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1717 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1718 
1719 /******************* Bit definition for CAN_TI1R register *******************/
1720 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1721 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1722 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1723 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1724 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1725 
1726 /******************* Bit definition for CAN_TDT1R register ******************/
1727 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1728 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1729 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1730 
1731 /******************* Bit definition for CAN_TDL1R register ******************/
1732 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1733 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1734 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1735 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1736 
1737 /******************* Bit definition for CAN_TDH1R register ******************/
1738 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1739 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1740 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1741 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1742 
1743 /******************* Bit definition for CAN_TI2R register *******************/
1744 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1745 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1746 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1747 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1748 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1749 
1750 /******************* Bit definition for CAN_TDT2R register ******************/
1751 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1752 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1753 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1754 
1755 /******************* Bit definition for CAN_TDL2R register ******************/
1756 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1757 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1758 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1759 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1760 
1761 /******************* Bit definition for CAN_TDH2R register ******************/
1762 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1763 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1764 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1765 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1766 
1767 /******************* Bit definition for CAN_RI0R register *******************/
1768 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1769 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1770 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1771 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1772 
1773 /******************* Bit definition for CAN_RDT0R register ******************/
1774 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1775 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1776 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1777 
1778 /******************* Bit definition for CAN_RDL0R register ******************/
1779 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1780 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1781 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1782 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1783 
1784 /******************* Bit definition for CAN_RDH0R register ******************/
1785 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1786 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1787 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1788 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1789 
1790 /******************* Bit definition for CAN_RI1R register *******************/
1791 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1792 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1793 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1794 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1795 
1796 /******************* Bit definition for CAN_RDT1R register ******************/
1797 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1798 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1799 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1800 
1801 /******************* Bit definition for CAN_RDL1R register ******************/
1802 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1803 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1804 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1805 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1806 
1807 /******************* Bit definition for CAN_RDH1R register ******************/
1808 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1809 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1810 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1811 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1812 
1813 /*!<CAN filter registers */
1814 /******************* Bit definition for CAN_FMR register ********************/
1815 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
1816 
1817 /******************* Bit definition for CAN_FM1R register *******************/
1818 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
1819 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
1820 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
1821 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
1822 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
1823 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
1824 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
1825 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
1826 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
1827 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
1828 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
1829 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
1830 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
1831 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
1832 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
1833 
1834 /******************* Bit definition for CAN_FS1R register *******************/
1835 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
1836 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
1837 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
1838 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
1839 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
1840 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
1841 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
1842 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
1843 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
1844 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
1845 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
1846 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
1847 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
1848 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
1849 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
1850 
1851 /****************** Bit definition for CAN_FFA1R register *******************/
1852 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
1853 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
1854 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
1855 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
1856 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
1857 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
1858 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
1859 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
1860 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
1861 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
1862 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
1863 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
1864 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
1865 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
1866 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
1867 
1868 /******************* Bit definition for CAN_FA1R register *******************/
1869 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
1870 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
1871 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
1872 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
1873 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
1874 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
1875 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
1876 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
1877 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
1878 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
1879 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
1880 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
1881 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
1882 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
1883 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
1884 
1885 /******************* Bit definition for CAN_F0R1 register *******************/
1886 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1887 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1888 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1889 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1890 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1891 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1892 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1893 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1894 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1895 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1896 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1897 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1898 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1899 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1900 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1901 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1902 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1903 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1904 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1905 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1906 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1907 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1908 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1909 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1910 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1911 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1912 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1913 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1914 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1915 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1916 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1917 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1918 
1919 /******************* Bit definition for CAN_F1R1 register *******************/
1920 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1921 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1922 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1923 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1924 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1925 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1926 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1927 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1928 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1929 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1930 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1931 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1932 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1933 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1934 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1935 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1936 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1937 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1938 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1939 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1940 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1941 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1942 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1943 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1944 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1945 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1946 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1947 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1948 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1949 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1950 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1951 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1952 
1953 /******************* Bit definition for CAN_F2R1 register *******************/
1954 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1955 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1956 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1957 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1958 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1959 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1960 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1961 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1962 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1963 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1964 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1965 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1966 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1967 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1968 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1969 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1970 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1971 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1972 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1973 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1974 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1975 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1976 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1977 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1978 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1979 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1980 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1981 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1982 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1983 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1984 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1985 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1986 
1987 /******************* Bit definition for CAN_F3R1 register *******************/
1988 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1989 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1990 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1991 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1992 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1993 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1994 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1995 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1996 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1997 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1998 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1999 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2000 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2001 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2002 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2003 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2004 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2005 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2006 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2007 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2008 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2009 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2010 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2011 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2012 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2013 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2014 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2015 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2016 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2017 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2018 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2019 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2020 
2021 /******************* Bit definition for CAN_F4R1 register *******************/
2022 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2023 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2024 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2025 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2026 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2027 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2028 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2029 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2030 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2031 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2032 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2033 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2034 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2035 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2036 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2037 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2038 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2039 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2040 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2041 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2042 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2043 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2044 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2045 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2046 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2047 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2048 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2049 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2050 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2051 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2052 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2053 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2054 
2055 /******************* Bit definition for CAN_F5R1 register *******************/
2056 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2057 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2058 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2059 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2060 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2061 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2062 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2063 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2064 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2065 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2066 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2067 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2068 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2069 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2070 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2071 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2072 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2073 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2074 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2075 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2076 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2077 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2078 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2079 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2080 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2081 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2082 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2083 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2084 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2085 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2086 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2087 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2088 
2089 /******************* Bit definition for CAN_F6R1 register *******************/
2090 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2091 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2092 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2093 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2094 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2095 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2096 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2097 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2098 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2099 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2100 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2101 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2102 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2103 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2104 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2105 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2106 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2107 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2108 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2109 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2110 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2111 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2112 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2113 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2114 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2115 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2116 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2117 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2118 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2119 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2120 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2121 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2122 
2123 /******************* Bit definition for CAN_F7R1 register *******************/
2124 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2125 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2126 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2127 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2128 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2129 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2130 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2131 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2132 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2133 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2134 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2135 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2136 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2137 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2138 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2139 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2140 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2141 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2142 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2143 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2144 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2145 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2146 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2147 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2148 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2149 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2150 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2151 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2152 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2153 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2154 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2155 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2156 
2157 /******************* Bit definition for CAN_F8R1 register *******************/
2158 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2159 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2160 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2161 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2162 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2163 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2164 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2165 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2166 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2167 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2168 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2169 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2170 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2171 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2172 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2173 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2174 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2175 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2176 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2177 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2178 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2179 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2180 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2181 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2182 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2183 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2184 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2185 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2186 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2187 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2188 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2189 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2190 
2191 /******************* Bit definition for CAN_F9R1 register *******************/
2192 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2193 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2194 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2195 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2196 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2197 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2198 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2199 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2200 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2201 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2202 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2203 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2204 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2205 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2206 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2207 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2208 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2209 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2210 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2211 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2212 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2213 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2214 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2215 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2216 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2217 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2218 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2219 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2220 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2221 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2222 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2223 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2224 
2225 /******************* Bit definition for CAN_F10R1 register ******************/
2226 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2227 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2228 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2229 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2230 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2231 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2232 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2233 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2234 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2235 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2236 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2237 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2238 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2239 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2240 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2241 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2242 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2243 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2244 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2245 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2246 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2247 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2248 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2249 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2250 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2251 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2252 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2253 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2254 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2255 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2256 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2257 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2258 
2259 /******************* Bit definition for CAN_F11R1 register ******************/
2260 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2261 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2262 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2263 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2264 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2265 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2266 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2267 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2268 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2269 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2270 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2271 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2272 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2273 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2274 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2275 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2276 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2277 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2278 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2279 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2280 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2281 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2282 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2283 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2284 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2285 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2286 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2287 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2288 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2289 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2290 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2291 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2292 
2293 /******************* Bit definition for CAN_F12R1 register ******************/
2294 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2295 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2296 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2297 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2298 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2299 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2300 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2301 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2302 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2303 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2304 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2305 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2306 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2307 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2308 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2309 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2310 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2311 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2312 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2313 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2314 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2315 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2316 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2317 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2318 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2319 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2320 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2321 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2322 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2323 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2324 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2325 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2326 
2327 /******************* Bit definition for CAN_F13R1 register ******************/
2328 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2329 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2330 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2331 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2332 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2333 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2334 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2335 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2336 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2337 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2338 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2339 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2340 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2341 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2342 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2343 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2344 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2345 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2346 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2347 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2348 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2349 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2350 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2351 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2352 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2353 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2354 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2355 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2356 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2357 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2358 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2359 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2360 
2361 /******************* Bit definition for CAN_F0R2 register *******************/
2362 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2363 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2364 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2365 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2366 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2367 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2368 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2369 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2370 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2371 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2372 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2373 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2374 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2375 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2376 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2377 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2378 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2379 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2380 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2381 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2382 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2383 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2384 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2385 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2386 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2387 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2388 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2389 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2390 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2391 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2392 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2393 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2394 
2395 /******************* Bit definition for CAN_F1R2 register *******************/
2396 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2397 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2398 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2399 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2400 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2401 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2402 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2403 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2404 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2405 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2406 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2407 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2408 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2409 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2410 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2411 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2412 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2413 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2414 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2415 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2416 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2417 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2418 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2419 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2420 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2421 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2422 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2423 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2424 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2425 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2426 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2427 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2428 
2429 /******************* Bit definition for CAN_F2R2 register *******************/
2430 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2431 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2432 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2433 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2434 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2435 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2436 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2437 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2438 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2439 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2440 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2441 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2442 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2443 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2444 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2445 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2446 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2447 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2448 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2449 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2450 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2451 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2452 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2453 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2454 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2455 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2456 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2457 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2458 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2459 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2460 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2461 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2462 
2463 /******************* Bit definition for CAN_F3R2 register *******************/
2464 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2465 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2466 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2467 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2468 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2469 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2470 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2471 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2472 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2473 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2474 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2475 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2476 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2477 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2478 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2479 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2480 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2481 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2482 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2483 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2484 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2485 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2486 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2487 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2488 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2489 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2490 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2491 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2492 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2493 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2494 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2495 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2496 
2497 /******************* Bit definition for CAN_F4R2 register *******************/
2498 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2499 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2500 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2501 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2502 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2503 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2504 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2505 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2506 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2507 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2508 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2509 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2510 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2511 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2512 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2513 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2514 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2515 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2516 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2517 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2518 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2519 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2520 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2521 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2522 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2523 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2524 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2525 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2526 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2527 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2528 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2529 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2530 
2531 /******************* Bit definition for CAN_F5R2 register *******************/
2532 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2533 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2534 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2535 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2536 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2537 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2538 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2539 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2540 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2541 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2542 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2543 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2544 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2545 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2546 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2547 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2548 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2549 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2550 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2551 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2552 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2553 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2554 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2555 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2556 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2557 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2558 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2559 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2560 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2561 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2562 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2563 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2564 
2565 /******************* Bit definition for CAN_F6R2 register *******************/
2566 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2567 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2568 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2569 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2570 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2571 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2572 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2573 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2574 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2575 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2576 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2577 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2578 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2579 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2580 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2581 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2582 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2583 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2584 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2585 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2586 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2587 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2588 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2589 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2590 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2591 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2592 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2593 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2594 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2595 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2596 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2597 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2598 
2599 /******************* Bit definition for CAN_F7R2 register *******************/
2600 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2601 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2602 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2603 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2604 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2605 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2606 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2607 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2608 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2609 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2610 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2611 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2612 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2613 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2614 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2615 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2616 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2617 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2618 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2619 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2620 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2621 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2622 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2623 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2624 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2625 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2626 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2627 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2628 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2629 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2630 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2631 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2632 
2633 /******************* Bit definition for CAN_F8R2 register *******************/
2634 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2635 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2636 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2637 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2638 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2639 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2640 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2641 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2642 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2643 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2644 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2645 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2646 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2647 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2648 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2649 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2650 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2651 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2652 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2653 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2654 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2655 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2656 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2657 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2658 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2659 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2660 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2661 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2662 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2663 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2664 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2665 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2666 
2667 /******************* Bit definition for CAN_F9R2 register *******************/
2668 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2669 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2670 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2671 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2672 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2673 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2674 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2675 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2676 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2677 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2678 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2679 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2680 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2681 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2682 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2683 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2684 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2685 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2686 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2687 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2688 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2689 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2690 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2691 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2692 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2693 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2694 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2695 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2696 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2697 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2698 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2699 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2700 
2701 /******************* Bit definition for CAN_F10R2 register ******************/
2702 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2703 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2704 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2705 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2706 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2707 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2708 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2709 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2710 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2711 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2712 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2713 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2714 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2715 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2716 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2717 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2718 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2719 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2720 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2721 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2722 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2723 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2724 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2725 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2726 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2727 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2728 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2729 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2730 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2731 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2732 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2733 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2734 
2735 /******************* Bit definition for CAN_F11R2 register ******************/
2736 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2737 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2738 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2739 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2740 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2741 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2742 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2743 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2744 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2745 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2746 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2747 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2748 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2749 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2750 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2751 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2752 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2753 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2754 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2755 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2756 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2757 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2758 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2759 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2760 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2761 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2762 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2763 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2764 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2765 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2766 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2767 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2768 
2769 /******************* Bit definition for CAN_F12R2 register ******************/
2770 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2771 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2772 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2773 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2774 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2775 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2776 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2777 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2778 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2779 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2780 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2781 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2782 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2783 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2784 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2785 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2786 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2787 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2788 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2789 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2790 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2791 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2792 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2793 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2794 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2795 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2796 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2797 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2798 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2799 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2800 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2801 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2802 
2803 /******************* Bit definition for CAN_F13R2 register ******************/
2804 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2805 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2806 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2807 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2808 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2809 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2810 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2811 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2812 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2813 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2814 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2815 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2816 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2817 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2818 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2819 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2820 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2821 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2822 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2823 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2824 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2825 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2826 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2827 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2828 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2829 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2830 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2831 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2832 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2833 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2834 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2835 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2836 
2837 /******************************************************************************/
2838 /* */
2839 /* CRC calculation unit */
2840 /* */
2841 /******************************************************************************/
2842 /******************* Bit definition for CRC_DR register *********************/
2843 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
2844 
2845 
2846 /******************* Bit definition for CRC_IDR register ********************/
2847 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
2848 
2849 
2850 /******************** Bit definition for CRC_CR register ********************/
2851 #define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
2852 
2853 /******************************************************************************/
2854 /* */
2855 /* Crypto Processor */
2856 /* */
2857 /******************************************************************************/
2858 /******************* Bits definition for CRYP_CR register ********************/
2859 #define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
2860 
2861 #define CRYP_CR_ALGOMODE ((uint32_t)0x00000038)
2862 #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
2863 #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
2864 #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
2865 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
2866 #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
2867 #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
2868 #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
2869 #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
2870 #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
2871 #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
2872 #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
2873 
2874 #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
2875 #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
2876 #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
2877 #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
2878 #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
2879 #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
2880 #define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
2881 #define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
2882 /****************** Bits definition for CRYP_SR register *********************/
2883 #define CRYP_SR_IFEM ((uint32_t)0x00000001)
2884 #define CRYP_SR_IFNF ((uint32_t)0x00000002)
2885 #define CRYP_SR_OFNE ((uint32_t)0x00000004)
2886 #define CRYP_SR_OFFU ((uint32_t)0x00000008)
2887 #define CRYP_SR_BUSY ((uint32_t)0x00000010)
2888 /****************** Bits definition for CRYP_DMACR register ******************/
2889 #define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
2890 #define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
2891 /***************** Bits definition for CRYP_IMSCR register ******************/
2892 #define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
2893 #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
2894 /****************** Bits definition for CRYP_RISR register *******************/
2895 #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
2896 #define CRYP_RISR_INRIS ((uint32_t)0x00000002)
2897 /****************** Bits definition for CRYP_MISR register *******************/
2898 #define CRYP_MISR_INMIS ((uint32_t)0x00000001)
2899 #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
2900 
2901 /******************************************************************************/
2902 /* */
2903 /* Digital to Analog Converter */
2904 /* */
2905 /******************************************************************************/
2906 /******************** Bit definition for DAC_CR register ********************/
2907 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
2908 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
2909 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
2910 
2911 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
2912 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
2913 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
2914 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
2915 
2916 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2917 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
2918 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
2919 
2920 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2921 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
2922 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
2923 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
2924 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
2925 
2926 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
2927 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
2928 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
2929 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
2930 
2931 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
2932 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
2933 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
2934 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
2935 
2936 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2937 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
2938 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
2939 
2940 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2941 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
2942 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
2943 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
2944 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
2945 
2946 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
2947 
2948 /***************** Bit definition for DAC_SWTRIGR register ******************/
2949 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
2950 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
2951 
2952 /***************** Bit definition for DAC_DHR12R1 register ******************/
2953 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
2954 
2955 /***************** Bit definition for DAC_DHR12L1 register ******************/
2956 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
2957 
2958 /****************** Bit definition for DAC_DHR8R1 register ******************/
2959 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
2960 
2961 /***************** Bit definition for DAC_DHR12R2 register ******************/
2962 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
2963 
2964 /***************** Bit definition for DAC_DHR12L2 register ******************/
2965 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
2966 
2967 /****************** Bit definition for DAC_DHR8R2 register ******************/
2968 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
2969 
2970 /***************** Bit definition for DAC_DHR12RD register ******************/
2971 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
2972 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
2973 
2974 /***************** Bit definition for DAC_DHR12LD register ******************/
2975 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
2976 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
2977 
2978 /****************** Bit definition for DAC_DHR8RD register ******************/
2979 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
2980 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
2981 
2982 /******************* Bit definition for DAC_DOR1 register *******************/
2983 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
2984 
2985 /******************* Bit definition for DAC_DOR2 register *******************/
2986 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
2987 
2988 /******************** Bit definition for DAC_SR register ********************/
2989 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
2990 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
2991 
2992 /******************************************************************************/
2993 /* */
2994 /* Debug MCU */
2995 /* */
2996 /******************************************************************************/
2997 
2998 /******************************************************************************/
2999 /* */
3000 /* DCMI */
3001 /* */
3002 /******************************************************************************/
3003 /******************** Bits definition for DCMI_CR register ******************/
3004 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
3005 #define DCMI_CR_CM ((uint32_t)0x00000002)
3006 #define DCMI_CR_CROP ((uint32_t)0x00000004)
3007 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
3008 #define DCMI_CR_ESS ((uint32_t)0x00000010)
3009 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
3010 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
3011 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
3012 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
3013 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
3014 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
3015 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
3016 #define DCMI_CR_CRE ((uint32_t)0x00001000)
3017 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
3018 
3019 /******************** Bits definition for DCMI_SR register ******************/
3020 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
3021 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
3022 #define DCMI_SR_FNE ((uint32_t)0x00000004)
3023 
3024 /******************** Bits definition for DCMI_RISR register ****************/
3025 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
3026 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
3027 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
3028 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
3029 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
3030 
3031 /******************** Bits definition for DCMI_IER register *****************/
3032 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
3033 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
3034 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
3035 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
3036 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
3037 
3038 /******************** Bits definition for DCMI_MISR register ****************/
3039 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
3040 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
3041 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
3042 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
3043 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
3044 
3045 /******************** Bits definition for DCMI_ICR register *****************/
3046 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
3047 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
3048 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
3049 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
3050 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
3051 
3052 /******************************************************************************/
3053 /* */
3054 /* DMA Controller */
3055 /* */
3056 /******************************************************************************/
3057 /******************** Bits definition for DMA_SxCR register *****************/
3058 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
3059 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
3060 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
3061 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
3062 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
3063 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
3064 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
3065 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
3066 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
3067 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
3068 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
3069 #define DMA_SxCR_CT ((uint32_t)0x00080000)
3070 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
3071 #define DMA_SxCR_PL ((uint32_t)0x00030000)
3072 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
3073 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
3074 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
3075 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
3076 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
3077 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
3078 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
3079 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
3080 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
3081 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
3082 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
3083 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
3084 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
3085 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
3086 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
3087 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
3088 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
3089 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
3090 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
3091 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
3092 #define DMA_SxCR_EN ((uint32_t)0x00000001)
3093 
3094 /******************** Bits definition for DMA_SxCNDTR register **************/
3095 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
3096 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
3097 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
3098 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
3099 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
3100 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
3101 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
3102 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
3103 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
3104 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
3105 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
3106 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
3107 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
3108 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
3109 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
3110 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
3111 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
3112 
3113 /******************** Bits definition for DMA_SxFCR register ****************/
3114 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
3115 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
3116 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
3117 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
3118 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
3119 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
3120 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
3121 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
3122 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
3123 
3124 /******************** Bits definition for DMA_LISR register *****************/
3125 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
3126 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
3127 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
3128 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
3129 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
3130 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
3131 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
3132 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
3133 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
3134 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
3135 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
3136 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
3137 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
3138 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
3139 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
3140 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
3141 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
3142 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
3143 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
3144 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
3145 
3146 /******************** Bits definition for DMA_HISR register *****************/
3147 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
3148 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
3149 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
3150 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
3151 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
3152 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
3153 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
3154 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
3155 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
3156 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
3157 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
3158 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
3159 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
3160 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
3161 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
3162 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
3163 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
3164 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
3165 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
3166 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
3167 
3168 /******************** Bits definition for DMA_LIFCR register ****************/
3169 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
3170 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
3171 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
3172 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
3173 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
3174 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
3175 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
3176 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
3177 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
3178 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
3179 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
3180 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
3181 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
3182 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
3183 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
3184 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
3185 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
3186 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
3187 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
3188 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
3189 
3190 /******************** Bits definition for DMA_HIFCR register ****************/
3191 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
3192 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
3193 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
3194 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
3195 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
3196 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
3197 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
3198 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
3199 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
3200 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
3201 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
3202 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
3203 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
3204 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
3205 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
3206 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
3207 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
3208 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
3209 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
3210 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
3211 
3212 /******************************************************************************/
3213 /* */
3214 /* External Interrupt/Event Controller */
3215 /* */
3216 /******************************************************************************/
3217 /******************* Bit definition for EXTI_IMR register *******************/
3218 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
3219 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
3220 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
3221 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
3222 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
3223 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
3224 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
3225 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
3226 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
3227 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
3228 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
3229 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
3230 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
3231 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
3232 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
3233 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
3234 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
3235 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
3236 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
3237 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
3238 
3239 /******************* Bit definition for EXTI_EMR register *******************/
3240 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
3241 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
3242 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
3243 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
3244 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
3245 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
3246 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
3247 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
3248 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
3249 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
3250 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
3251 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
3252 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
3253 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
3254 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
3255 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
3256 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
3257 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
3258 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
3259 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
3260 
3261 /****************** Bit definition for EXTI_RTSR register *******************/
3262 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
3263 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
3264 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
3265 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
3266 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
3267 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
3268 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
3269 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
3270 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
3271 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
3272 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
3273 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
3274 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
3275 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
3276 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
3277 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
3278 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
3279 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
3280 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
3281 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
3282 
3283 /****************** Bit definition for EXTI_FTSR register *******************/
3284 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
3285 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
3286 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
3287 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
3288 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
3289 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
3290 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
3291 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
3292 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
3293 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
3294 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
3295 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
3296 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
3297 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
3298 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
3299 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
3300 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
3301 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
3302 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
3303 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
3304 
3305 /****************** Bit definition for EXTI_SWIER register ******************/
3306 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
3307 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
3308 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
3309 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
3310 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
3311 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
3312 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
3313 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
3314 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
3315 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
3316 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
3317 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
3318 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
3319 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
3320 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
3321 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
3322 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
3323 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
3324 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
3325 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
3326 
3327 /******************* Bit definition for EXTI_PR register ********************/
3328 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
3329 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
3330 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
3331 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
3332 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
3333 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
3334 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
3335 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
3336 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
3337 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
3338 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
3339 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
3340 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
3341 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
3342 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
3343 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
3344 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
3345 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
3346 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
3347 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
3348 
3349 /******************************************************************************/
3350 /* */
3351 /* FLASH */
3352 /* */
3353 /******************************************************************************/
3354 /******************* Bits definition for FLASH_ACR register *****************/
3355 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007)
3356 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
3357 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
3358 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
3359 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
3360 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
3361 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
3362 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
3363 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
3364 
3365 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
3366 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
3367 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
3368 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
3369 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
3370 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
3371 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
3372 
3373 /******************* Bits definition for FLASH_SR register ******************/
3374 #define FLASH_SR_EOP ((uint32_t)0x00000001)
3375 #define FLASH_SR_SOP ((uint32_t)0x00000002)
3376 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
3377 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
3378 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
3379 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
3380 #define FLASH_SR_BSY ((uint32_t)0x00010000)
3381 
3382 /******************* Bits definition for FLASH_CR register ******************/
3383 #define FLASH_CR_PG ((uint32_t)0x00000001)
3384 #define FLASH_CR_SER ((uint32_t)0x00000002)
3385 #define FLASH_CR_MER ((uint32_t)0x00000004)
3386 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
3387 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
3388 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
3389 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
3390 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
3391 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
3392 #define FLASH_CR_STRT ((uint32_t)0x00010000)
3393 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
3394 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
3395 
3396 /******************* Bits definition for FLASH_OPTCR register ***************/
3397 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
3398 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
3399 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
3400 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
3401 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
3402 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
3403 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
3404 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
3405 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
3406 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
3407 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
3408 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
3409 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
3410 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
3411 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
3412 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
3413 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
3414 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
3415 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
3416 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
3417 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
3418 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
3419 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
3420 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
3421 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
3422 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
3423 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
3424 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
3425 
3426 /******************************************************************************/
3427 /* */
3428 /* Flexible Static Memory Controller */
3429 /* */
3430 /******************************************************************************/
3431 /****************** Bit definition for FSMC_BCR1 register *******************/
3432 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3433 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3434 
3435 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3436 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3437 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3438 
3439 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3440 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3441 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3442 
3443 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3444 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3445 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3446 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3447 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3448 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3449 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3450 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3451 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3452 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3453 
3454 /****************** Bit definition for FSMC_BCR2 register *******************/
3455 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3456 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3457 
3458 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3459 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3460 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3461 
3462 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3463 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3464 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3465 
3466 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3467 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3468 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3469 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3470 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3471 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3472 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3473 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3474 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3475 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3476 
3477 /****************** Bit definition for FSMC_BCR3 register *******************/
3478 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3479 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3480 
3481 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3482 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3483 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3484 
3485 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3486 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3487 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3488 
3489 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3490 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3491 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */
3492 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3493 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3494 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3495 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3496 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3497 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3498 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3499 
3500 /****************** Bit definition for FSMC_BCR4 register *******************/
3501 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3502 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3503 
3504 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3505 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3506 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3507 
3508 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3509 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3510 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3511 
3512 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3513 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3514 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3515 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3516 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3517 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3518 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3519 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3520 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3521 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3522 
3523 /****************** Bit definition for FSMC_BTR1 register ******************/
3524 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3525 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3526 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3527 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3528 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3529 
3530 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3531 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3532 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3533 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3534 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3535 
3536 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3537 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3538 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3539 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3540 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3541 
3542 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3543 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3544 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3545 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3546 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3547 
3548 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3549 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3550 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3551 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3552 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3553 
3554 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3555 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3556 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3557 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3558 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3559 
3560 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3561 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3562 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3563 
3564 /****************** Bit definition for FSMC_BTR2 register *******************/
3565 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3566 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3567 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3568 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3569 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3570 
3571 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3572 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3573 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3574 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3575 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3576 
3577 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3578 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3579 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3580 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3581 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3582 
3583 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3584 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3585 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3586 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3587 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3588 
3589 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3590 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3591 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3592 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3593 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3594 
3595 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3596 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3597 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3598 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3599 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3600 
3601 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3602 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3603 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3604 
3605 /******************* Bit definition for FSMC_BTR3 register *******************/
3606 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3607 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3608 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3609 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3610 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3611 
3612 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3613 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3614 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3615 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3616 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3617 
3618 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3619 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3620 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3621 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3622 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3623 
3624 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3625 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3626 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3627 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3628 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3629 
3630 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3631 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3632 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3633 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3634 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3635 
3636 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3637 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3638 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3639 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3640 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3641 
3642 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3643 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3644 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3645 
3646 /****************** Bit definition for FSMC_BTR4 register *******************/
3647 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3648 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3649 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3650 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3651 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3652 
3653 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3654 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3655 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3656 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3657 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3658 
3659 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3660 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3661 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3662 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3663 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3664 
3665 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3666 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3667 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3668 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3669 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3670 
3671 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3672 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3673 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3674 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3675 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3676 
3677 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3678 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3679 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3680 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3681 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3682 
3683 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3684 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3685 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3686 
3687 /****************** Bit definition for FSMC_BWTR1 register ******************/
3688 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3689 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3690 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3691 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3692 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3693 
3694 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3695 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3696 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3697 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3698 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3699 
3700 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3701 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3702 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3703 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3704 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3705 
3706 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3707 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3708 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3709 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3710 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3711 
3712 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3713 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3714 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3715 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3716 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3717 
3718 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3719 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3720 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3721 
3722 /****************** Bit definition for FSMC_BWTR2 register ******************/
3723 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3724 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3725 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3726 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3727 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3728 
3729 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3730 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3731 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3732 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3733 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3734 
3735 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3736 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3737 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3738 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3739 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3740 
3741 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3742 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3743 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
3744 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3745 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3746 
3747 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3748 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3749 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3750 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3751 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3752 
3753 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3754 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3755 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3756 
3757 /****************** Bit definition for FSMC_BWTR3 register ******************/
3758 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3759 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3760 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3761 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3762 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3763 
3764 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3765 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3766 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3767 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3768 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3769 
3770 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3771 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3772 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3773 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3774 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3775 
3776 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3777 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3778 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3779 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3780 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3781 
3782 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3783 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3784 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3785 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3786 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3787 
3788 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3789 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3790 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3791 
3792 /****************** Bit definition for FSMC_BWTR4 register ******************/
3793 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3794 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3795 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3796 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3797 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3798 
3799 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3800 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3801 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3802 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3803 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3804 
3805 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3806 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3807 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3808 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3809 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3810 
3811 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3812 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3813 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3814 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3815 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3816 
3817 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3818 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3819 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3820 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3821 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3822 
3823 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3824 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3825 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3826 
3827 /****************** Bit definition for FSMC_PCR2 register *******************/
3828 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
3829 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
3830 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
3831 
3832 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
3833 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3834 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3835 
3836 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
3837 
3838 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
3839 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3840 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3841 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3842 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
3843 
3844 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
3845 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
3846 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
3847 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
3848 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
3849 
3850 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
3851 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3852 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3853 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3854 
3855 /****************** Bit definition for FSMC_PCR3 register *******************/
3856 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
3857 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
3858 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
3859 
3860 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
3861 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3862 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3863 
3864 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
3865 
3866 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
3867 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3868 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3869 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3870 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
3871 
3872 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
3873 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
3874 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
3875 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
3876 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
3877 
3878 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
3879 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3880 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3881 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3882 
3883 /****************** Bit definition for FSMC_PCR4 register *******************/
3884 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
3885 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
3886 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
3887 
3888 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
3889 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3890 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3891 
3892 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
3893 
3894 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
3895 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3896 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3897 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3898 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
3899 
3900 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
3901 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
3902 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
3903 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
3904 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
3905 
3906 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
3907 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3908 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3909 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3910 
3911 /******************* Bit definition for FSMC_SR2 register *******************/
3912 #define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
3913 #define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
3914 #define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
3915 #define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
3916 #define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
3917 #define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
3918 #define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
3919 
3920 /******************* Bit definition for FSMC_SR3 register *******************/
3921 #define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
3922 #define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
3923 #define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
3924 #define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
3925 #define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
3926 #define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
3927 #define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
3928 
3929 /******************* Bit definition for FSMC_SR4 register *******************/
3930 #define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
3931 #define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
3932 #define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
3933 #define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
3934 #define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
3935 #define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
3936 #define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
3937 
3938 /****************** Bit definition for FSMC_PMEM2 register ******************/
3939 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
3940 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3941 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3942 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3943 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3944 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3945 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
3946 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
3947 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
3948 
3949 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
3950 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3951 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3952 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3953 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3954 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3955 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3956 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3957 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3958 
3959 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
3960 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3961 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3962 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3963 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3964 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
3965 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
3966 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
3967 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
3968 
3969 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
3970 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3971 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3972 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3973 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3974 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
3975 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
3976 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
3977 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
3978 
3979 /****************** Bit definition for FSMC_PMEM3 register ******************/
3980 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
3981 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3982 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3983 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3984 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3985 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3986 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
3987 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
3988 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
3989 
3990 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
3991 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3992 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3993 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3994 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3995 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3996 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3997 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3998 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3999 
4000 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
4001 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4002 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4003 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4004 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4005 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4006 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4007 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4008 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4009 
4010 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
4011 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4012 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4013 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4014 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4015 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4016 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4017 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4018 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4019 
4020 /****************** Bit definition for FSMC_PMEM4 register ******************/
4021 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
4022 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4023 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4024 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4025 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4026 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4027 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4028 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4029 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4030 
4031 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
4032 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4033 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4034 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4035 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4036 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4037 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4038 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4039 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4040 
4041 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
4042 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4043 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4044 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4045 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4046 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4047 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4048 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4049 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4050 
4051 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
4052 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4053 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4054 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4055 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4056 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4057 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4058 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4059 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4060 
4061 /****************** Bit definition for FSMC_PATT2 register ******************/
4062 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
4063 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4064 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4065 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4066 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4067 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4068 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4069 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4070 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4071 
4072 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
4073 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4074 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4075 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4076 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4077 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4078 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4079 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4080 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4081 
4082 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
4083 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4084 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4085 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4086 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4087 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4088 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4089 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4090 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4091 
4092 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
4093 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4094 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4095 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4096 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4097 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4098 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4099 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4100 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4101 
4102 /****************** Bit definition for FSMC_PATT3 register ******************/
4103 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
4104 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4105 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4106 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4107 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4108 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4109 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4110 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4111 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4112 
4113 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
4114 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4115 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4116 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4117 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4118 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4119 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4120 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4121 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4122 
4123 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
4124 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4125 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4126 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4127 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4128 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4129 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4130 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4131 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4132 
4133 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
4134 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4135 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4136 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4137 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4138 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4139 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4140 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4141 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4142 
4143 /****************** Bit definition for FSMC_PATT4 register ******************/
4144 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
4145 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4146 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4147 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4148 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4149 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4150 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4151 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4152 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4153 
4154 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
4155 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4156 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4157 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4158 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4159 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4160 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4161 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4162 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4163 
4164 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
4165 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4166 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4167 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4168 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4169 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4170 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4171 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4172 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4173 
4174 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
4175 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4176 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4177 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4178 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4179 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4180 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4181 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4182 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4183 
4184 /****************** Bit definition for FSMC_PIO4 register *******************/
4185 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
4186 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4187 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4188 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4189 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4190 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4191 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4192 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4193 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4194 
4195 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
4196 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4197 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4198 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4199 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4200 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4201 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4202 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4203 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4204 
4205 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
4206 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4207 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4208 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4209 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4210 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4211 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4212 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4213 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4214 
4215 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
4216 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4217 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4218 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4219 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4220 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4221 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4222 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4223 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4224 
4225 /****************** Bit definition for FSMC_ECCR2 register ******************/
4226 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4227 
4228 /****************** Bit definition for FSMC_ECCR3 register ******************/
4229 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4230 
4231 /******************************************************************************/
4232 /* */
4233 /* General Purpose I/O */
4234 /* */
4235 /******************************************************************************/
4236 /****************** Bits definition for GPIO_MODER register *****************/
4237 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
4238 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
4239 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
4240 
4241 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
4242 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
4243 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
4244 
4245 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
4246 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
4247 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
4248 
4249 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
4250 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
4251 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
4252 
4253 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
4254 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
4255 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
4256 
4257 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
4258 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
4259 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
4260 
4261 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
4262 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
4263 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
4264 
4265 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
4266 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
4267 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
4268 
4269 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
4270 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
4271 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
4272 
4273 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
4274 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
4275 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
4276 
4277 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
4278 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
4279 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
4280 
4281 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
4282 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
4283 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
4284 
4285 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
4286 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
4287 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
4288 
4289 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
4290 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
4291 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
4292 
4293 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
4294 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
4295 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
4296 
4297 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
4298 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
4299 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
4300 
4301 /****************** Bits definition for GPIO_OTYPER register ****************/
4302 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
4303 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
4304 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
4305 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
4306 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
4307 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
4308 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
4309 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
4310 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
4311 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
4312 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
4313 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
4314 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
4315 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
4316 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
4317 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
4318 
4319 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4320 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
4321 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
4322 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
4323 
4324 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
4325 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
4326 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
4327 
4328 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
4329 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
4330 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
4331 
4332 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
4333 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
4334 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
4335 
4336 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
4337 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
4338 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
4339 
4340 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
4341 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
4342 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
4343 
4344 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
4345 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
4346 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
4347 
4348 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
4349 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
4350 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
4351 
4352 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
4353 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
4354 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
4355 
4356 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
4357 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
4358 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
4359 
4360 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
4361 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
4362 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
4363 
4364 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
4365 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
4366 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
4367 
4368 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
4369 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
4370 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
4371 
4372 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
4373 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
4374 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
4375 
4376 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
4377 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
4378 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
4379 
4380 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
4381 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
4382 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
4383 
4384 /****************** Bits definition for GPIO_PUPDR register *****************/
4385 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
4386 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
4387 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
4388 
4389 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
4390 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
4391 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
4392 
4393 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
4394 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
4395 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
4396 
4397 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
4398 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
4399 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
4400 
4401 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
4402 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
4403 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
4404 
4405 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
4406 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
4407 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
4408 
4409 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
4410 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
4411 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
4412 
4413 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
4414 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
4415 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
4416 
4417 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
4418 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
4419 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
4420 
4421 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
4422 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
4423 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
4424 
4425 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
4426 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
4427 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
4428 
4429 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
4430 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
4431 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
4432 
4433 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
4434 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
4435 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
4436 
4437 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
4438 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
4439 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
4440 
4441 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
4442 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
4443 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
4444 
4445 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
4446 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
4447 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
4448 
4449 /****************** Bits definition for GPIO_IDR register *******************/
4450 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
4451 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
4452 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
4453 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
4454 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
4455 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
4456 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
4457 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
4458 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
4459 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
4460 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
4461 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
4462 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
4463 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
4464 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
4465 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
4466 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
4467 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
4468 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
4469 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
4470 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
4471 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
4472 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
4473 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
4474 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
4475 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
4476 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
4477 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
4478 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
4479 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
4480 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
4481 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
4482 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
4483 
4484 /****************** Bits definition for GPIO_ODR register *******************/
4485 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
4486 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
4487 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
4488 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
4489 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
4490 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
4491 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
4492 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
4493 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
4494 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
4495 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
4496 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
4497 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
4498 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
4499 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
4500 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
4501 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
4502 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
4503 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
4504 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
4505 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
4506 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
4507 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
4508 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
4509 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
4510 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
4511 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
4512 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
4513 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
4514 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
4515 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
4516 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
4517 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
4518 
4519 /****************** Bits definition for GPIO_BSRR register ******************/
4520 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
4521 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
4522 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
4523 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
4524 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
4525 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
4526 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
4527 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
4528 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
4529 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
4530 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
4531 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
4532 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
4533 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
4534 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
4535 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
4536 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
4537 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
4538 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
4539 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
4540 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
4541 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
4542 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
4543 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
4544 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
4545 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
4546 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
4547 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
4548 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
4549 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
4550 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
4551 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
4552 
4553 /******************************************************************************/
4554 /* */
4555 /* HASH */
4556 /* */
4557 /******************************************************************************/
4558 /****************** Bits definition for HASH_CR register ********************/
4559 #define HASH_CR_INIT ((uint32_t)0x00000004)
4560 #define HASH_CR_DMAE ((uint32_t)0x00000008)
4561 #define HASH_CR_DATATYPE ((uint32_t)0x00000030)
4562 #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
4563 #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
4564 #define HASH_CR_MODE ((uint32_t)0x00000040)
4565 #define HASH_CR_ALGO ((uint32_t)0x00000080)
4566 #define HASH_CR_NBW ((uint32_t)0x00000F00)
4567 #define HASH_CR_NBW_0 ((uint32_t)0x00000100)
4568 #define HASH_CR_NBW_1 ((uint32_t)0x00000200)
4569 #define HASH_CR_NBW_2 ((uint32_t)0x00000400)
4570 #define HASH_CR_NBW_3 ((uint32_t)0x00000800)
4571 #define HASH_CR_DINNE ((uint32_t)0x00001000)
4572 #define HASH_CR_LKEY ((uint32_t)0x00010000)
4573 
4574 /****************** Bits definition for HASH_STR register *******************/
4575 #define HASH_STR_NBW ((uint32_t)0x0000001F)
4576 #define HASH_STR_NBW_0 ((uint32_t)0x00000001)
4577 #define HASH_STR_NBW_1 ((uint32_t)0x00000002)
4578 #define HASH_STR_NBW_2 ((uint32_t)0x00000004)
4579 #define HASH_STR_NBW_3 ((uint32_t)0x00000008)
4580 #define HASH_STR_NBW_4 ((uint32_t)0x00000010)
4581 #define HASH_STR_DCAL ((uint32_t)0x00000100)
4582 
4583 /****************** Bits definition for HASH_IMR register *******************/
4584 #define HASH_IMR_DINIM ((uint32_t)0x00000001)
4585 #define HASH_IMR_DCIM ((uint32_t)0x00000002)
4586 
4587 /****************** Bits definition for HASH_SR register ********************/
4588 #define HASH_SR_DINIS ((uint32_t)0x00000001)
4589 #define HASH_SR_DCIS ((uint32_t)0x00000002)
4590 #define HASH_SR_DMAS ((uint32_t)0x00000004)
4591 #define HASH_SR_BUSY ((uint32_t)0x00000008)
4592 
4593 /******************************************************************************/
4594 /* */
4595 /* Inter-integrated Circuit Interface */
4596 /* */
4597 /******************************************************************************/
4598 /******************* Bit definition for I2C_CR1 register ********************/
4599 #define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
4600 #define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
4601 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
4602 #define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
4603 #define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
4604 #define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
4605 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
4606 #define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
4607 #define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
4608 #define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
4609 #define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
4610 #define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
4611 #define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
4612 #define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
4613 
4614 /******************* Bit definition for I2C_CR2 register ********************/
4615 #define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
4616 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
4617 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
4618 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
4619 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
4620 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
4621 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
4622 
4623 #define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
4624 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
4625 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
4626 #define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
4627 #define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
4628 
4629 /******************* Bit definition for I2C_OAR1 register *******************/
4630 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
4631 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
4632 
4633 #define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
4634 #define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
4635 #define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
4636 #define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
4637 #define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
4638 #define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
4639 #define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
4640 #define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
4641 #define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
4642 #define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
4643 
4644 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
4645 
4646 /******************* Bit definition for I2C_OAR2 register *******************/
4647 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
4648 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
4649 
4650 /******************** Bit definition for I2C_DR register ********************/
4651 #define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
4652 
4653 /******************* Bit definition for I2C_SR1 register ********************/
4654 #define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
4655 #define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
4656 #define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
4657 #define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
4658 #define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
4659 #define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
4660 #define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
4661 #define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
4662 #define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
4663 #define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
4664 #define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
4665 #define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
4666 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
4667 #define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
4668 
4669 /******************* Bit definition for I2C_SR2 register ********************/
4670 #define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
4671 #define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
4672 #define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
4673 #define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
4674 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
4675 #define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
4676 #define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
4677 #define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
4678 
4679 /******************* Bit definition for I2C_CCR register ********************/
4680 #define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
4681 #define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
4682 #define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
4683 
4684 /****************** Bit definition for I2C_TRISE register *******************/
4685 #define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
4686 
4687 /******************************************************************************/
4688 /* */
4689 /* Independent WATCHDOG */
4690 /* */
4691 /******************************************************************************/
4692 /******************* Bit definition for IWDG_KR register ********************/
4693 #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
4694 
4695 /******************* Bit definition for IWDG_PR register ********************/
4696 #define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
4697 #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
4698 #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
4699 #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
4700 
4701 /******************* Bit definition for IWDG_RLR register *******************/
4702 #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
4703 
4704 /******************* Bit definition for IWDG_SR register ********************/
4705 #define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
4706 #define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
4707 
4708 /******************************************************************************/
4709 /* */
4710 /* Power Control */
4711 /* */
4712 /******************************************************************************/
4713 /******************** Bit definition for PWR_CR register ********************/
4714 #define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
4715 #define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
4716 #define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
4717 #define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
4718 #define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
4719 
4720 #define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
4721 #define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
4722 #define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
4723 #define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
4724 
4725 
4726 /*!< PVD level configuration */
4727 #define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
4728 #define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
4729 #define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
4730 #define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
4731 #define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
4732 #define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
4733 #define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
4734 #define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
4735 
4736 #define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
4737 #define PWR_CR_FPDS ((uint16_t)0x0200) /*!< Flash power down in Stop mode */
4738 #define PWR_CR_VOS ((uint16_t)0x4000) /*!< Regulator voltage scaling output selection */
4739 /* Legacy define */
4740 #define PWR_CR_PMODE PWR_CR_VOS
4741 
4742 /******************* Bit definition for PWR_CSR register ********************/
4743 #define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
4744 #define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
4745 #define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
4746 #define PWR_CSR_BRR ((uint16_t)0x0008) /*!< Backup regulator ready */
4747 #define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
4748 #define PWR_CSR_BRE ((uint16_t)0x0200) /*!< Backup regulator enable */
4749 #define PWR_CSR_VOSRDY ((uint16_t)0x4000) /*!< Regulator voltage scaling output selection ready */
4750 /* Legacy define */
4751 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
4752 
4753 /******************************************************************************/
4754 /* */
4755 /* Reset and Clock Control */
4756 /* */
4757 /******************************************************************************/
4758 /******************** Bit definition for RCC_CR register ********************/
4759 #define RCC_CR_HSION ((uint32_t)0x00000001)
4760 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
4761 
4762 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
4763 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
4764 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
4765 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
4766 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
4767 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
4768 
4769 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
4770 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
4771 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
4772 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
4773 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
4774 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
4775 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
4776 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
4777 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
4778 
4779 #define RCC_CR_HSEON ((uint32_t)0x00010000)
4780 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
4781 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
4782 #define RCC_CR_CSSON ((uint32_t)0x00080000)
4783 #define RCC_CR_PLLON ((uint32_t)0x01000000)
4784 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
4785 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
4786 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
4787 
4788 /******************** Bit definition for RCC_PLLCFGR register ***************/
4789 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
4790 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
4791 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
4792 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
4793 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
4794 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
4795 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
4796 
4797 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
4798 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
4799 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
4800 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
4801 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
4802 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
4803 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
4804 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
4805 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
4806 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
4807 
4808 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
4809 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
4810 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
4811 
4812 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
4813 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
4814 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
4815 
4816 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
4817 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
4818 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
4819 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
4820 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
4821 
4822 /******************** Bit definition for RCC_CFGR register ******************/
4823 /*!< SW configuration */
4824 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
4825 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4826 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4827 
4828 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
4829 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
4830 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
4831 
4832 /*!< SWS configuration */
4833 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
4834 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
4835 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
4836 
4837 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
4838 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
4839 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
4840 
4841 /*!< HPRE configuration */
4842 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
4843 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
4844 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
4845 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
4846 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
4847 
4848 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
4849 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
4850 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
4851 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
4852 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
4853 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
4854 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
4855 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
4856 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
4857 
4858 /*!< PPRE1 configuration */
4859 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
4860 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4861 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4862 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4863 
4864 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
4865 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
4866 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
4867 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
4868 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
4869 
4870 /*!< PPRE2 configuration */
4871 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
4872 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
4873 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
4874 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
4875 
4876 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
4877 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
4878 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
4879 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
4880 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
4881 
4882 /*!< RTCPRE configuration */
4883 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
4884 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
4885 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
4886 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
4887 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
4888 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
4889 
4890 /*!< MCO1 configuration */
4891 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
4892 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
4893 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
4894 
4895 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
4896 
4897 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
4898 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
4899 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
4900 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
4901 
4902 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
4903 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
4904 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
4905 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
4906 
4907 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
4908 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
4909 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
4910 
4911 /******************** Bit definition for RCC_CIR register *******************/
4912 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
4913 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
4914 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
4915 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
4916 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
4917 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
4918 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
4919 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
4920 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
4921 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
4922 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
4923 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
4924 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
4925 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
4926 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
4927 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
4928 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
4929 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
4930 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
4931 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
4932 
4933 /******************** Bit definition for RCC_AHB1RSTR register **************/
4934 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
4935 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
4936 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
4937 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
4938 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
4939 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
4940 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
4941 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
4942 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
4943 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
4944 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
4945 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
4946 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
4947 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
4948 
4949 /******************** Bit definition for RCC_AHB2RSTR register **************/
4950 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
4951 #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
4952 #define RCC_AHB2RSTR_HSAHRST ((uint32_t)0x00000020)
4953 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
4954 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
4955 
4956 /******************** Bit definition for RCC_AHB3RSTR register **************/
4957 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
4958 
4959 /******************** Bit definition for RCC_APB1RSTR register **************/
4960 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
4961 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
4962 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
4963 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
4964 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
4965 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
4966 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
4967 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
4968 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
4969 #define RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800)
4970 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00008000)
4971 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00010000)
4972 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
4973 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
4974 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
4975 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
4976 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
4977 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
4978 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
4979 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
4980 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
4981 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
4982 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
4983 
4984 /******************** Bit definition for RCC_APB2RSTR register **************/
4985 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
4986 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
4987 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
4988 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
4989 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
4990 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
4991 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
4992 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
4993 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
4994 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
4995 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
4996 /* Old SPI1RST bit definition, maintained for legacy purpose */
4997 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
4998 
4999 /******************** Bit definition for RCC_AHB1ENR register ***************/
5000 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
5001 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
5002 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
5003 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
5004 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
5005 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
5006 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
5007 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
5008 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
5009 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
5010 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
5011 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
5012 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
5013 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
5014 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
5015 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
5016 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
5017 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
5018 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
5019 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
5020 
5021 /******************** Bit definition for RCC_AHB2ENR register ***************/
5022 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
5023 #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
5024 #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
5025 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
5026 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
5027 
5028 /******************** Bit definition for RCC_AHB3ENR register ***************/
5029 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
5030 
5031 /******************** Bit definition for RCC_APB1ENR register ***************/
5032 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
5033 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
5034 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
5035 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
5036 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
5037 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
5038 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
5039 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
5040 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
5041 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
5042 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
5043 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
5044 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
5045 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
5046 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
5047 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
5048 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
5049 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
5050 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
5051 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
5052 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
5053 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
5054 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
5055 
5056 /******************** Bit definition for RCC_APB2ENR register ***************/
5057 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
5058 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
5059 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
5060 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
5061 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
5062 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
5063 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
5064 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
5065 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
5066 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
5067 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
5068 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
5069 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
5070 
5071 /******************** Bit definition for RCC_AHB1LPENR register *************/
5072 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
5073 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
5074 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
5075 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
5076 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
5077 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
5078 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
5079 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
5080 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
5081 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
5082 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
5083 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
5084 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
5085 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
5086 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
5087 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
5088 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
5089 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
5090 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
5091 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
5092 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
5093 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
5094 
5095 /******************** Bit definition for RCC_AHB2LPENR register *************/
5096 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
5097 #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
5098 #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
5099 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
5100 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
5101 
5102 /******************** Bit definition for RCC_AHB3LPENR register *************/
5103 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
5104 
5105 /******************** Bit definition for RCC_APB1LPENR register *************/
5106 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
5107 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
5108 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
5109 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
5110 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
5111 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
5112 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
5113 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
5114 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
5115 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
5116 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
5117 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
5118 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
5119 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
5120 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
5121 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
5122 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
5123 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
5124 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
5125 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
5126 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
5127 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
5128 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
5129 
5130 /******************** Bit definition for RCC_APB2LPENR register *************/
5131 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
5132 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
5133 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
5134 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
5135 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
5136 #define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
5137 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
5138 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
5139 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
5140 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
5141 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
5142 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
5143 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
5144 
5145 /******************** Bit definition for RCC_BDCR register ******************/
5146 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
5147 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
5148 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
5149 
5150 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
5151 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
5152 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
5153 
5154 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
5155 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
5156 
5157 /******************** Bit definition for RCC_CSR register *******************/
5158 #define RCC_CSR_LSION ((uint32_t)0x00000001)
5159 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
5160 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
5161 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
5162 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
5163 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
5164 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
5165 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
5166 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
5167 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
5168 
5169 /******************** Bit definition for RCC_SSCGR register *****************/
5170 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
5171 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
5172 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
5173 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
5174 
5175 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5176 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
5177 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
5178 
5179 /******************************************************************************/
5180 /* */
5181 /* RNG */
5182 /* */
5183 /******************************************************************************/
5184 /******************** Bits definition for RNG_CR register *******************/
5185 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
5186 #define RNG_CR_IE ((uint32_t)0x00000008)
5187 
5188 /******************** Bits definition for RNG_SR register *******************/
5189 #define RNG_SR_DRDY ((uint32_t)0x00000001)
5190 #define RNG_SR_CECS ((uint32_t)0x00000002)
5191 #define RNG_SR_SECS ((uint32_t)0x00000004)
5192 #define RNG_SR_CEIS ((uint32_t)0x00000020)
5193 #define RNG_SR_SEIS ((uint32_t)0x00000040)
5194 
5195 /******************************************************************************/
5196 /* */
5197 /* Real-Time Clock (RTC) */
5198 /* */
5199 /******************************************************************************/
5200 /******************** Bits definition for RTC_TR register *******************/
5201 #define RTC_TR_PM ((uint32_t)0x00400000)
5202 #define RTC_TR_HT ((uint32_t)0x00300000)
5203 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
5204 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
5205 #define RTC_TR_HU ((uint32_t)0x000F0000)
5206 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
5207 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
5208 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
5209 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
5210 #define RTC_TR_MNT ((uint32_t)0x00007000)
5211 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
5212 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
5213 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
5214 #define RTC_TR_MNU ((uint32_t)0x00000F00)
5215 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
5216 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
5217 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
5218 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
5219 #define RTC_TR_ST ((uint32_t)0x00000070)
5220 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
5221 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
5222 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
5223 #define RTC_TR_SU ((uint32_t)0x0000000F)
5224 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
5225 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
5226 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
5227 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
5228 
5229 /******************** Bits definition for RTC_DR register *******************/
5230 #define RTC_DR_YT ((uint32_t)0x00F00000)
5231 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
5232 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
5233 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
5234 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
5235 #define RTC_DR_YU ((uint32_t)0x000F0000)
5236 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
5237 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
5238 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
5239 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
5240 #define RTC_DR_WDU ((uint32_t)0x0000E000)
5241 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
5242 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
5243 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
5244 #define RTC_DR_MT ((uint32_t)0x00001000)
5245 #define RTC_DR_MU ((uint32_t)0x00000F00)
5246 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
5247 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
5248 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
5249 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
5250 #define RTC_DR_DT ((uint32_t)0x00000030)
5251 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
5252 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
5253 #define RTC_DR_DU ((uint32_t)0x0000000F)
5254 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
5255 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
5256 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
5257 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
5258 
5259 /******************** Bits definition for RTC_CR register *******************/
5260 #define RTC_CR_COE ((uint32_t)0x00800000)
5261 #define RTC_CR_OSEL ((uint32_t)0x00600000)
5262 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
5263 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
5264 #define RTC_CR_POL ((uint32_t)0x00100000)
5265 #define RTC_CR_COSEL ((uint32_t)0x00080000)
5266 #define RTC_CR_BCK ((uint32_t)0x00040000)
5267 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
5268 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
5269 #define RTC_CR_TSIE ((uint32_t)0x00008000)
5270 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
5271 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
5272 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
5273 #define RTC_CR_TSE ((uint32_t)0x00000800)
5274 #define RTC_CR_WUTE ((uint32_t)0x00000400)
5275 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
5276 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
5277 #define RTC_CR_DCE ((uint32_t)0x00000080)
5278 #define RTC_CR_FMT ((uint32_t)0x00000040)
5279 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
5280 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
5281 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
5282 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
5283 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
5284 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
5285 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
5286 
5287 /******************** Bits definition for RTC_ISR register ******************/
5288 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
5289 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
5290 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
5291 #define RTC_ISR_TSF ((uint32_t)0x00000800)
5292 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
5293 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
5294 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
5295 #define RTC_ISR_INIT ((uint32_t)0x00000080)
5296 #define RTC_ISR_INITF ((uint32_t)0x00000040)
5297 #define RTC_ISR_RSF ((uint32_t)0x00000020)
5298 #define RTC_ISR_INITS ((uint32_t)0x00000010)
5299 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
5300 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
5301 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
5302 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
5303 
5304 /******************** Bits definition for RTC_PRER register *****************/
5305 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
5306 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
5307 
5308 /******************** Bits definition for RTC_WUTR register *****************/
5309 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
5310 
5311 /******************** Bits definition for RTC_CALIBR register ***************/
5312 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
5313 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
5314 
5315 /******************** Bits definition for RTC_ALRMAR register ***************/
5316 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
5317 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
5318 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
5319 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
5320 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
5321 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
5322 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
5323 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
5324 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
5325 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
5326 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
5327 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
5328 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
5329 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
5330 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
5331 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
5332 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
5333 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
5334 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
5335 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
5336 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
5337 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
5338 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
5339 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
5340 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
5341 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
5342 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
5343 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
5344 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
5345 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
5346 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
5347 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
5348 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
5349 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
5350 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
5351 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
5352 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
5353 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
5354 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
5355 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
5356 
5357 /******************** Bits definition for RTC_ALRMBR register ***************/
5358 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
5359 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
5360 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
5361 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
5362 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
5363 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
5364 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
5365 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
5366 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
5367 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
5368 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
5369 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
5370 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
5371 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
5372 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
5373 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
5374 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
5375 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
5376 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
5377 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
5378 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
5379 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
5380 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
5381 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
5382 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
5383 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
5384 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
5385 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
5386 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
5387 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
5388 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
5389 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
5390 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
5391 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
5392 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
5393 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
5394 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
5395 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
5396 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
5397 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
5398 
5399 /******************** Bits definition for RTC_WPR register ******************/
5400 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
5401 
5402 /******************** Bits definition for RTC_SSR register ******************/
5403 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
5404 
5405 /******************** Bits definition for RTC_SHIFTR register ***************/
5406 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
5407 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
5408 
5409 /******************** Bits definition for RTC_TSTR register *****************/
5410 #define RTC_TSTR_PM ((uint32_t)0x00400000)
5411 #define RTC_TSTR_HT ((uint32_t)0x00300000)
5412 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
5413 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
5414 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
5415 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
5416 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
5417 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
5418 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
5419 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
5420 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
5421 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
5422 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
5423 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
5424 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
5425 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
5426 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
5427 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
5428 #define RTC_TSTR_ST ((uint32_t)0x00000070)
5429 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
5430 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
5431 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
5432 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
5433 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
5434 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
5435 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
5436 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
5437 
5438 /******************** Bits definition for RTC_TSDR register *****************/
5439 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
5440 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
5441 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
5442 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
5443 #define RTC_TSDR_MT ((uint32_t)0x00001000)
5444 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
5445 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
5446 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
5447 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
5448 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
5449 #define RTC_TSDR_DT ((uint32_t)0x00000030)
5450 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
5451 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
5452 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
5453 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
5454 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
5455 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
5456 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
5457 
5458 /******************** Bits definition for RTC_TSSSR register ****************/
5459 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
5460 
5461 /******************** Bits definition for RTC_CAL register *****************/
5462 #define RTC_CALR_CALP ((uint32_t)0x00008000)
5463 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
5464 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
5465 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
5466 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
5467 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
5468 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
5469 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
5470 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
5471 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
5472 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
5473 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
5474 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
5475 
5476 /******************** Bits definition for RTC_TAFCR register ****************/
5477 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
5478 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
5479 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
5480 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
5481 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
5482 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
5483 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
5484 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
5485 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
5486 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
5487 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
5488 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
5489 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
5490 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
5491 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
5492 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
5493 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
5494 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
5495 
5496 /******************** Bits definition for RTC_ALRMASSR register *************/
5497 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
5498 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
5499 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
5500 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
5501 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
5502 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
5503 
5504 /******************** Bits definition for RTC_ALRMBSSR register *************/
5505 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
5506 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
5507 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
5508 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
5509 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
5510 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
5511 
5512 /******************** Bits definition for RTC_BKP0R register ****************/
5513 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
5514 
5515 /******************** Bits definition for RTC_BKP1R register ****************/
5516 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
5517 
5518 /******************** Bits definition for RTC_BKP2R register ****************/
5519 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
5520 
5521 /******************** Bits definition for RTC_BKP3R register ****************/
5522 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
5523 
5524 /******************** Bits definition for RTC_BKP4R register ****************/
5525 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
5526 
5527 /******************** Bits definition for RTC_BKP5R register ****************/
5528 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
5529 
5530 /******************** Bits definition for RTC_BKP6R register ****************/
5531 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
5532 
5533 /******************** Bits definition for RTC_BKP7R register ****************/
5534 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
5535 
5536 /******************** Bits definition for RTC_BKP8R register ****************/
5537 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
5538 
5539 /******************** Bits definition for RTC_BKP9R register ****************/
5540 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
5541 
5542 /******************** Bits definition for RTC_BKP10R register ***************/
5543 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
5544 
5545 /******************** Bits definition for RTC_BKP11R register ***************/
5546 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
5547 
5548 /******************** Bits definition for RTC_BKP12R register ***************/
5549 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
5550 
5551 /******************** Bits definition for RTC_BKP13R register ***************/
5552 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
5553 
5554 /******************** Bits definition for RTC_BKP14R register ***************/
5555 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
5556 
5557 /******************** Bits definition for RTC_BKP15R register ***************/
5558 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
5559 
5560 /******************** Bits definition for RTC_BKP16R register ***************/
5561 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
5562 
5563 /******************** Bits definition for RTC_BKP17R register ***************/
5564 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
5565 
5566 /******************** Bits definition for RTC_BKP18R register ***************/
5567 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
5568 
5569 /******************** Bits definition for RTC_BKP19R register ***************/
5570 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
5571 
5572 /******************************************************************************/
5573 /* */
5574 /* SD host Interface */
5575 /* */
5576 /******************************************************************************/
5577 /****************** Bit definition for SDIO_POWER register ******************/
5578 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
5579 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
5580 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
5581 
5582 /****************** Bit definition for SDIO_CLKCR register ******************/
5583 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
5584 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
5585 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
5586 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
5587 
5588 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
5589 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
5590 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
5591 
5592 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
5593 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
5594 
5595 /******************* Bit definition for SDIO_ARG register *******************/
5596 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
5597 
5598 /******************* Bit definition for SDIO_CMD register *******************/
5599 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
5600 
5601 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
5602 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
5603 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
5604 
5605 #define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
5606 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
5607 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
5608 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
5609 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
5610 #define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
5611 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
5612 
5613 /***************** Bit definition for SDIO_RESPCMD register *****************/
5614 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
5615 
5616 /****************** Bit definition for SDIO_RESP0 register ******************/
5617 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5618 
5619 /****************** Bit definition for SDIO_RESP1 register ******************/
5620 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5621 
5622 /****************** Bit definition for SDIO_RESP2 register ******************/
5623 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5624 
5625 /****************** Bit definition for SDIO_RESP3 register ******************/
5626 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5627 
5628 /****************** Bit definition for SDIO_RESP4 register ******************/
5629 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5630 
5631 /****************** Bit definition for SDIO_DTIMER register *****************/
5632 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
5633 
5634 /****************** Bit definition for SDIO_DLEN register *******************/
5635 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
5636 
5637 /****************** Bit definition for SDIO_DCTRL register ******************/
5638 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
5639 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
5640 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
5641 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
5642 
5643 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
5644 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
5645 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
5646 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
5647 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
5648 
5649 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
5650 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
5651 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
5652 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
5653 
5654 /****************** Bit definition for SDIO_DCOUNT register *****************/
5655 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
5656 
5657 /****************** Bit definition for SDIO_STA register ********************/
5658 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
5659 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
5660 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
5661 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
5662 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
5663 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
5664 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
5665 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
5666 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
5667 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
5668 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
5669 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
5670 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
5671 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
5672 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
5673 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
5674 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
5675 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
5676 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
5677 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
5678 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
5679 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
5680 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
5681 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
5682 
5683 /******************* Bit definition for SDIO_ICR register *******************/
5684 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
5685 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
5686 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
5687 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
5688 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
5689 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
5690 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
5691 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
5692 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
5693 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
5694 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
5695 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
5696 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
5697 
5698 /****************** Bit definition for SDIO_MASK register *******************/
5699 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
5700 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
5701 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
5702 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
5703 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
5704 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
5705 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
5706 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
5707 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
5708 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
5709 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
5710 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
5711 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
5712 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
5713 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
5714 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
5715 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
5716 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
5717 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
5718 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
5719 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
5720 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
5721 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
5722 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
5723 
5724 /***************** Bit definition for SDIO_FIFOCNT register *****************/
5725 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
5726 
5727 /****************** Bit definition for SDIO_FIFO register *******************/
5728 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
5729 
5730 /******************************************************************************/
5731 /* */
5732 /* Serial Peripheral Interface */
5733 /* */
5734 /******************************************************************************/
5735 /******************* Bit definition for SPI_CR1 register ********************/
5736 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
5737 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
5738 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
5739 
5740 #define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
5741 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
5742 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
5743 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
5744 
5745 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
5746 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
5747 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
5748 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
5749 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
5750 #define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
5751 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
5752 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
5753 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
5754 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
5755 
5756 /******************* Bit definition for SPI_CR2 register ********************/
5757 #define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
5758 #define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
5759 #define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
5760 #define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
5761 #define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
5762 #define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
5763 
5764 /******************** Bit definition for SPI_SR register ********************/
5765 #define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
5766 #define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
5767 #define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
5768 #define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
5769 #define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
5770 #define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
5771 #define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
5772 #define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
5773 
5774 /******************** Bit definition for SPI_DR register ********************/
5775 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
5776 
5777 /******************* Bit definition for SPI_CRCPR register ******************/
5778 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
5779 
5780 /****************** Bit definition for SPI_RXCRCR register ******************/
5781 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
5782 
5783 /****************** Bit definition for SPI_TXCRCR register ******************/
5784 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
5785 
5786 /****************** Bit definition for SPI_I2SCFGR register *****************/
5787 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
5788 
5789 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
5790 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
5791 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
5792 
5793 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
5794 
5795 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
5796 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
5797 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
5798 
5799 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
5800 
5801 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
5802 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
5803 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
5804 
5805 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
5806 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
5807 
5808 /****************** Bit definition for SPI_I2SPR register *******************/
5809 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
5810 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
5811 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
5812 
5813 /******************************************************************************/
5814 /* */
5815 /* SYSCFG */
5816 /* */
5817 /******************************************************************************/
5818 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
5819 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!<SYSCFG_Memory Remap Config */
5820 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
5821 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
5822 
5823 /****************** Bit definition for SYSCFG_PMC register ******************/
5824 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
5825 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
5826 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
5827 
5828 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
5829 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */
5830 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
5831 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
5832 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!<EXTI 3 configuration */
5833 /**
5834  * @brief EXTI0 configuration
5835  */
5836 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */
5837 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */
5838 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */
5839 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */
5840 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */
5841 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */
5842 #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */
5843 #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */
5844 #define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */
5845 /**
5846  * @brief EXTI1 configuration
5847  */
5848 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */
5849 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */
5850 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */
5851 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */
5852 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */
5853 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */
5854 #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */
5855 #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */
5856 #define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */
5857 /**
5858  * @brief EXTI2 configuration
5859  */
5860 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */
5861 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */
5862 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */
5863 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */
5864 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */
5865 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */
5866 #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */
5867 #define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */
5868 #define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */
5869 /**
5870  * @brief EXTI3 configuration
5871  */
5872 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */
5873 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */
5874 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */
5875 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */
5876 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */
5877 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */
5878 #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */
5879 #define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */
5880 #define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */
5881 
5882 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5883 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!<EXTI 4 configuration */
5884 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
5885 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
5886 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!<EXTI 7 configuration */
5887 /**
5888  * @brief EXTI4 configuration
5889  */
5890 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */
5891 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */
5892 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */
5893 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */
5894 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */
5895 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */
5896 #define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */
5897 #define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */
5898 #define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */
5899 /**
5900  * @brief EXTI5 configuration
5901  */
5902 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */
5903 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */
5904 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */
5905 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */
5906 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */
5907 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */
5908 #define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */
5909 #define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */
5910 #define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */
5911 /**
5912  * @brief EXTI6 configuration
5913  */
5914 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */
5915 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */
5916 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */
5917 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */
5918 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */
5919 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */
5920 #define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */
5921 #define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */
5922 #define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */
5923 /**
5924  * @brief EXTI7 configuration
5925  */
5926 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */
5927 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */
5928 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */
5929 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */
5930 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */
5931 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */
5932 #define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */
5933 #define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */
5934 #define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */
5935 
5936 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
5937 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!<EXTI 8 configuration */
5938 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
5939 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
5940 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!<EXTI 11 configuration */
5941 
5942 /**
5943  * @brief EXTI8 configuration
5944  */
5945 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */
5946 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */
5947 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */
5948 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */
5949 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */
5950 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */
5951 #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */
5952 #define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */
5953 #define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */
5954 /**
5955  * @brief EXTI9 configuration
5956  */
5957 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */
5958 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */
5959 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */
5960 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */
5961 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */
5962 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */
5963 #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */
5964 #define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */
5965 #define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */
5966 /**
5967  * @brief EXTI10 configuration
5968  */
5969 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */
5970 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */
5971 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */
5972 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */
5973 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */
5974 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */
5975 #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */
5976 #define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */
5977 #define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */
5978 /**
5979  * @brief EXTI11 configuration
5980  */
5981 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */
5982 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */
5983 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */
5984 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */
5985 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */
5986 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */
5987 #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */
5988 #define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */
5989 #define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */
5990 
5991 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
5992 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!<EXTI 12 configuration */
5993 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
5994 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
5995 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!<EXTI 15 configuration */
5996 /**
5997  * @brief EXTI12 configuration
5998  */
5999 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */
6000 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */
6001 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */
6002 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */
6003 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */
6004 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */
6005 #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */
6006 #define SYSCFG_EXTICR3_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */
6007 /**
6008  * @brief EXTI13 configuration
6009  */
6010 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */
6011 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */
6012 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */
6013 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */
6014 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */
6015 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */
6016 #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */
6017 #define SYSCFG_EXTICR3_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */
6018 /**
6019  * @brief EXTI14 configuration
6020  */
6021 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */
6022 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */
6023 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */
6024 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */
6025 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */
6026 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */
6027 #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */
6028 #define SYSCFG_EXTICR3_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */
6029 /**
6030  * @brief EXTI15 configuration
6031  */
6032 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */
6033 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */
6034 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */
6035 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */
6036 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */
6037 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */
6038 #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */
6039 #define SYSCFG_EXTICR3_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */
6040 
6041 /****************** Bit definition for SYSCFG_CMPCR register ****************/
6042 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
6043 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
6044 
6045 /******************************************************************************/
6046 /* */
6047 /* TIM */
6048 /* */
6049 /******************************************************************************/
6050 /******************* Bit definition for TIM_CR1 register ********************/
6051 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
6052 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
6053 #define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
6054 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
6055 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
6056 
6057 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
6058 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
6059 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
6060 
6061 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
6062 
6063 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
6064 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
6065 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
6066 
6067 /******************* Bit definition for TIM_CR2 register ********************/
6068 #define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
6069 #define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
6070 #define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
6071 
6072 #define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
6073 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
6074 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
6075 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
6076 
6077 #define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
6078 #define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
6079 #define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
6080 #define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
6081 #define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
6082 #define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
6083 #define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
6084 #define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
6085 
6086 /******************* Bit definition for TIM_SMCR register *******************/
6087 #define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
6088 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
6089 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
6090 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
6091 
6092 #define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
6093 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
6094 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
6095 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
6096 
6097 #define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
6098 
6099 #define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
6100 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
6101 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
6102 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
6103 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
6104 
6105 #define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
6106 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
6107 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
6108 
6109 #define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
6110 #define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
6111 
6112 /******************* Bit definition for TIM_DIER register *******************/
6113 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
6114 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
6115 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
6116 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
6117 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
6118 #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
6119 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
6120 #define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
6121 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
6122 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
6123 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
6124 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
6125 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
6126 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
6127 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
6128 
6129 /******************** Bit definition for TIM_SR register ********************/
6130 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
6131 #define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
6132 #define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
6133 #define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
6134 #define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
6135 #define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
6136 #define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
6137 #define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
6138 #define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
6139 #define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
6140 #define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
6141 #define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
6142 
6143 /******************* Bit definition for TIM_EGR register ********************/
6144 #define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
6145 #define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
6146 #define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
6147 #define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
6148 #define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
6149 #define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
6150 #define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
6151 #define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
6152 
6153 /****************** Bit definition for TIM_CCMR1 register *******************/
6154 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
6155 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
6156 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
6157 
6158 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
6159 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
6160 
6161 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
6162 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
6163 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
6164 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
6165 
6166 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
6167 
6168 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
6169 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
6170 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
6171 
6172 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
6173 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
6174 
6175 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
6176 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
6177 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
6178 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
6179 
6180 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
6181 
6182 /*----------------------------------------------------------------------------*/
6183 
6184 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
6185 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
6186 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
6187 
6188 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
6189 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
6190 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
6191 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
6192 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
6193 
6194 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
6195 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
6196 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
6197 
6198 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
6199 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
6200 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
6201 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
6202 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
6203 
6204 /****************** Bit definition for TIM_CCMR2 register *******************/
6205 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
6206 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
6207 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
6208 
6209 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
6210 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
6211 
6212 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
6213 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
6214 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
6215 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
6216 
6217 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
6218 
6219 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
6220 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
6221 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
6222 
6223 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
6224 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
6225 
6226 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
6227 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
6228 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
6229 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
6230 
6231 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
6232 
6233 /*----------------------------------------------------------------------------*/
6234 
6235 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
6236 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
6237 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
6238 
6239 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
6240 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
6241 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
6242 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
6243 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
6244 
6245 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
6246 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
6247 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
6248 
6249 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
6250 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
6251 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
6252 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
6253 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
6254 
6255 /******************* Bit definition for TIM_CCER register *******************/
6256 #define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
6257 #define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
6258 #define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
6259 #define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
6260 #define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
6261 #define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
6262 #define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
6263 #define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
6264 #define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
6265 #define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
6266 #define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
6267 #define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
6268 #define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
6269 #define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
6270 #define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
6271 
6272 /******************* Bit definition for TIM_CNT register ********************/
6273 #define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
6274 
6275 /******************* Bit definition for TIM_PSC register ********************/
6276 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
6277 
6278 /******************* Bit definition for TIM_ARR register ********************/
6279 #define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
6280 
6281 /******************* Bit definition for TIM_RCR register ********************/
6282 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
6283 
6284 /******************* Bit definition for TIM_CCR1 register *******************/
6285 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
6286 
6287 /******************* Bit definition for TIM_CCR2 register *******************/
6288 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
6289 
6290 /******************* Bit definition for TIM_CCR3 register *******************/
6291 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
6292 
6293 /******************* Bit definition for TIM_CCR4 register *******************/
6294 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
6295 
6296 /******************* Bit definition for TIM_BDTR register *******************/
6297 #define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
6298 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
6299 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
6300 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
6301 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
6302 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
6303 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
6304 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
6305 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
6306 
6307 #define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
6308 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
6309 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
6310 
6311 #define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
6312 #define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
6313 #define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
6314 #define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
6315 #define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
6316 #define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
6317 
6318 /******************* Bit definition for TIM_DCR register ********************/
6319 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
6320 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
6321 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
6322 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
6323 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
6324 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
6325 
6326 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
6327 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
6328 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
6329 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
6330 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
6331 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
6332 
6333 /******************* Bit definition for TIM_DMAR register *******************/
6334 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
6335 
6336 /******************* Bit definition for TIM_OR register *********************/
6337 #define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
6338 #define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
6339 #define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
6340 #define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
6341 #define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*!<Bit 0 */
6342 #define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*!<Bit 1 */
6343 
6344 
6345 /******************************************************************************/
6346 /* */
6347 /* Universal Synchronous Asynchronous Receiver Transmitter */
6348 /* */
6349 /******************************************************************************/
6350 /******************* Bit definition for USART_SR register *******************/
6351 #define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
6352 #define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
6353 #define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
6354 #define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
6355 #define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
6356 #define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
6357 #define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
6358 #define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
6359 #define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
6360 #define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
6361 
6362 /******************* Bit definition for USART_DR register *******************/
6363 #define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
6364 
6365 /****************** Bit definition for USART_BRR register *******************/
6366 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
6367 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
6368 
6369 /****************** Bit definition for USART_CR1 register *******************/
6370 #define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
6371 #define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
6372 #define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
6373 #define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
6374 #define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
6375 #define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
6376 #define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
6377 #define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
6378 #define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
6379 #define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
6380 #define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
6381 #define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
6382 #define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
6383 #define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
6384 #define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversampling by 8 enable */
6385 
6386 /****************** Bit definition for USART_CR2 register *******************/
6387 #define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
6388 #define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
6389 #define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
6390 #define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
6391 #define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
6392 #define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
6393 #define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
6394 
6395 #define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
6396 #define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
6397 #define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
6398 
6399 #define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
6400 
6401 /****************** Bit definition for USART_CR3 register *******************/
6402 #define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
6403 #define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
6404 #define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
6405 #define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
6406 #define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
6407 #define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
6408 #define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
6409 #define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
6410 #define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
6411 #define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
6412 #define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
6413 #define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<USART One bit method enable */
6414 
6415 /****************** Bit definition for USART_GTPR register ******************/
6416 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
6417 #define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
6418 #define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
6419 #define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
6420 #define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
6421 #define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
6422 #define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
6423 #define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
6424 #define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
6425 
6426 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
6427 
6428 /******************************************************************************/
6429 /* */
6430 /* Window WATCHDOG */
6431 /* */
6432 /******************************************************************************/
6433 /******************* Bit definition for WWDG_CR register ********************/
6434 #define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
6435 #define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
6436 #define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
6437 #define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
6438 #define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
6439 #define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
6440 #define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
6441 #define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
6442 
6443 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
6444 
6445 /******************* Bit definition for WWDG_CFR register *******************/
6446 #define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
6447 #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
6448 #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
6449 #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
6450 #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
6451 #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
6452 #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
6453 #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
6454 
6455 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
6456 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
6457 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
6458 
6459 #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
6460 
6461 /******************* Bit definition for WWDG_SR register ********************/
6462 #define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
6463 
6464 
6465 /******************************************************************************/
6466 /* */
6467 /* DBG */
6468 /* */
6469 /******************************************************************************/
6470 /******************** Bit definition for DBGMCU_IDCODE register *************/
6471 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
6472 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
6473 
6474 /******************** Bit definition for DBGMCU_CR register *****************/
6475 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
6476 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
6477 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
6478 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
6479 
6480 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
6481 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
6482 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
6483 
6484 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
6485 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
6486 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
6487 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
6488 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
6489 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
6490 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
6491 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
6492 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
6493 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
6494 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
6495 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
6496 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
6497 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
6498 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
6499 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
6500 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
6501 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
6502 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
6503 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
6504 
6505 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
6506 #define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
6507 #define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
6508 #define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
6509 #define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
6510 #define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
6511 
6512 /******************************************************************************/
6513 /* */
6514 /* Ethernet MAC Registers bits definitions */
6515 /* */
6516 /******************************************************************************/
6517 /* Bit definition for Ethernet MAC Control Register register */
6518 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
6519 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
6520 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
6521 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
6522  #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
6523  #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
6524  #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
6525  #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
6526  #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
6527  #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
6528  #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
6529 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
6530 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
6531 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
6532 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
6533 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
6534 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
6535 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
6536 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
6537 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
6538  a transmission attempt during retries after a collision: 0 =< r <2^k */
6539  #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
6540  #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
6541  #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
6542  #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
6543 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
6544 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
6545 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
6546 
6547 /* Bit definition for Ethernet MAC Frame Filter Register */
6548 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
6549 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
6550 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
6551 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
6552 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
6553  #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
6554  #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
6555  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
6556 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
6557 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
6558 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
6559 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
6560 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
6561 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
6562 
6563 /* Bit definition for Ethernet MAC Hash Table High Register */
6564 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
6565 
6566 /* Bit definition for Ethernet MAC Hash Table Low Register */
6567 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
6568 
6569 /* Bit definition for Ethernet MAC MII Address Register */
6570 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
6571 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
6572 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
6573  #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
6574  #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
6575  #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
6576  #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
6577  #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
6578 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
6579 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
6580 
6581 /* Bit definition for Ethernet MAC MII Data Register */
6582 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
6583 
6584 /* Bit definition for Ethernet MAC Flow Control Register */
6585 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
6586 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
6587 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
6588  #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
6589  #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
6590  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
6591  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
6592 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
6593 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
6594 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
6595 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
6596 
6597 /* Bit definition for Ethernet MAC VLAN Tag Register */
6598 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
6599 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
6600 
6601 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
6602 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
6603 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
6604  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
6605 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
6606  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
6607  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
6608  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
6609  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
6610  RSVD - Filter1 Command - RSVD - Filter0 Command
6611  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
6612  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
6613  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
6614 
6615 /* Bit definition for Ethernet MAC PMT Control and Status Register */
6616 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
6617 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
6618 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
6619 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
6620 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
6621 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
6622 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
6623 
6624 /* Bit definition for Ethernet MAC Status Register */
6625 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
6626 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
6627 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
6628 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
6629 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
6630 
6631 /* Bit definition for Ethernet MAC Interrupt Mask Register */
6632 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
6633 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
6634 
6635 /* Bit definition for Ethernet MAC Address0 High Register */
6636 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
6637 
6638 /* Bit definition for Ethernet MAC Address0 Low Register */
6639 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
6640 
6641 /* Bit definition for Ethernet MAC Address1 High Register */
6642 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
6643 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
6644 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
6645  #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
6646  #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
6647  #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
6648  #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
6649  #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
6650  #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
6651 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
6652 
6653 /* Bit definition for Ethernet MAC Address1 Low Register */
6654 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
6655 
6656 /* Bit definition for Ethernet MAC Address2 High Register */
6657 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
6658 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
6659 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
6660  #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
6661  #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
6662  #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
6663  #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
6664  #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
6665  #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
6666 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
6667 
6668 /* Bit definition for Ethernet MAC Address2 Low Register */
6669 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
6670 
6671 /* Bit definition for Ethernet MAC Address3 High Register */
6672 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
6673 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
6674 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
6675  #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
6676  #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
6677  #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
6678  #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
6679  #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
6680  #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
6681 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
6682 
6683 /* Bit definition for Ethernet MAC Address3 Low Register */
6684 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
6685 
6686 /******************************************************************************/
6687 /* Ethernet MMC Registers bits definition */
6688 /******************************************************************************/
6689 
6690 /* Bit definition for Ethernet MMC Contol Register */
6691 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
6692 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
6693 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
6694 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
6695 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
6696 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
6697 
6698 /* Bit definition for Ethernet MMC Receive Interrupt Register */
6699 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
6700 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
6701 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
6702 
6703 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
6704 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
6705 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
6706 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
6707 
6708 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
6709 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
6710 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
6711 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
6712 
6713 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
6714 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
6715 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
6716 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
6717 
6718 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
6719 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
6720 
6721 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
6722 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
6723 
6724 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
6725 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
6726 
6727 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
6728 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
6729 
6730 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
6731 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
6732 
6733 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
6734 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
6735 
6736 /******************************************************************************/
6737 /* Ethernet PTP Registers bits definition */
6738 /******************************************************************************/
6739 
6740 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
6741 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
6742 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
6743 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
6744 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
6745 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
6746 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
6747 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
6748 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
6749 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
6750 
6751 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
6752 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
6753 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
6754 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
6755 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
6756 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
6757 
6758 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
6759 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
6760 
6761 /* Bit definition for Ethernet PTP Time Stamp High Register */
6762 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
6763 
6764 /* Bit definition for Ethernet PTP Time Stamp Low Register */
6765 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
6766 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
6767 
6768 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
6769 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
6770 
6771 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
6772 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
6773 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
6774 
6775 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
6776 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
6777 
6778 /* Bit definition for Ethernet PTP Target Time High Register */
6779 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
6780 
6781 /* Bit definition for Ethernet PTP Target Time Low Register */
6782 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
6783 
6784 /* Bit definition for Ethernet PTP Time Stamp Status Register */
6785 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
6786 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
6787 
6788 /******************************************************************************/
6789 /* Ethernet DMA Registers bits definition */
6790 /******************************************************************************/
6791 
6792 /* Bit definition for Ethernet DMA Bus Mode Register */
6793 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
6794 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
6795 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
6796 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
6797  #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
6798  #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
6799  #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
6800  #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
6801  #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
6802  #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
6803  #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
6804  #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
6805  #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
6806  #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
6807  #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
6808  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
6809 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
6810 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
6811  #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
6812  #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
6813  #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
6814  #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
6815 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
6816  #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
6817  #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
6818  #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
6819  #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
6820  #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
6821  #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
6822  #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
6823  #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
6824  #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
6825  #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
6826  #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
6827  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
6828 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
6829 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
6830 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
6831 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
6832 
6833 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
6834 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
6835 
6836 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
6837 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
6838 
6839 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
6840 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
6841 
6842 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
6843 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
6844 
6845 /* Bit definition for Ethernet DMA Status Register */
6846 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
6847 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
6848 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
6849 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
6850  /* combination with EBS[2:0] for GetFlagStatus function */
6851  #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
6852  #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
6853  #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
6854 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
6855  #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
6856  #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
6857  #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
6858  #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
6859  #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
6860  #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
6861 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
6862  #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
6863  #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
6864  #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
6865  #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
6866  #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
6867  #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
6868 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
6869 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
6870 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
6871 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
6872 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
6873 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
6874 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
6875 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
6876 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
6877 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
6878 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
6879 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
6880 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
6881 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
6882 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
6883 
6884 /* Bit definition for Ethernet DMA Operation Mode Register */
6885 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
6886 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
6887 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
6888 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
6889 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
6890 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
6891  #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
6892  #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
6893  #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
6894  #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
6895  #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
6896  #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
6897  #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
6898  #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
6899 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
6900 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
6901 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
6902 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
6903  #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
6904  #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
6905  #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
6906  #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
6907 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
6908 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
6909 
6910 /* Bit definition for Ethernet DMA Interrupt Enable Register */
6911 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
6912 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
6913 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
6914 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
6915 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
6916 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
6917 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
6918 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
6919 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
6920 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
6921 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
6922 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
6923 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
6924 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
6925 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
6926 
6927 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
6928 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
6929 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
6930 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
6931 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
6932 
6933 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
6934 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
6935 
6936 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
6937 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
6938 
6939 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
6940 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
6941 
6942 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
6943 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
6944 
6945 /**
6946  * @}
6947  */
6948 
6949  /**
6950  * @}
6951  */
6952 
6953 #ifdef USE_STDPERIPH_DRIVER
6954  #include "stm32/stm32f4xx_conf.h"
6955 #endif /* USE_STDPERIPH_DRIVER */
6956 
6957 /** @addtogroup Exported_macro
6958  * @{
6959  */
6960 
6961 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
6962 
6963 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
6964 
6965 #define READ_BIT(REG, BIT) ((REG) & (BIT))
6966 
6967 #define CLEAR_REG(REG) ((REG) = (0x0))
6968 
6969 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
6970 
6971 #define READ_REG(REG) ((REG))
6972 
6973 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
6974 
6975 /**
6976  * @}
6977  */
6978 
6979 #ifdef __cplusplus
6980 }
6981 #endif /* __cplusplus */
6982 
6983 #endif /* __STM32F4xx_H */
6984 
6985 /**
6986  * @}
6987  */
6988 
6989  /**
6990  * @}
6991  */
6992 
6993 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
SDIO_TypeDef::FIFO
__IO uint32_t FIFO
Definition: stm32f4xx.h:829
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition: stm32f4xx.h:346
FLASH_TypeDef::OPTCR
__IO uint32_t OPTCR
Definition: stm32f4xx.h:577
USART_TypeDef::DR
__IO uint16_t DR
Definition: stm32f4xx.h:910
RTC_TypeDef::TR
__IO uint32_t TR
Definition: stm32f4xx.h:762
SDIO_TypeDef::RESP1
__I uint32_t RESP1
Definition: stm32f4xx.h:815
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f4xx.h:422
RTC_TypeDef::BKP16R
__IO uint32_t BKP16R
Definition: stm32f4xx.h:798
DMA1_Stream3_IRQn
Definition: stm32f4xx.h:153
RTC_TypeDef::WUTR
__IO uint32_t WUTR
Definition: stm32f4xx.h:767
DCMI_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:443
HASH_TypeDef::STR
__IO uint32_t STR
Definition: stm32f4xx.h:971
SVCall_IRQn
Definition: stm32f4xx.h:134
CRC_TypeDef
CRC calculation unit.
Definition: stm32f4xx.h:394
SPI_TypeDef::RESERVED8
uint16_t RESERVED8
Definition: stm32f4xx.h:855
DCMI_TypeDef::IER
__IO uint32_t IER
Definition: stm32f4xx.h:446
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition: stm32f4xx.h:311
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition: stm32f4xx.h:772
RCC_TypeDef::AHB2RSTR
__IO uint32_t AHB2RSTR
Definition: stm32f4xx.h:729
ADC_TypeDef::JOFR2
__IO uint32_t JOFR2
Definition: stm32f4xx.h:301
OTG_HS_EP1_OUT_IRQn
Definition: stm32f4xx.h:213
TIM5_IRQn
Definition: stm32f4xx.h:189
NonMaskableInt_IRQn
Definition: stm32f4xx.h:130
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f4xx.h:382
FLASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32f4xx.h:575
SysTick_IRQn
Definition: stm32f4xx.h:137
SPI_TypeDef::RESERVED5
uint16_t RESERVED5
Definition: stm32f4xx.h:849
HASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32f4xx.h:974
GPIO_TypeDef::MODER
__IO uint32_t MODER
Definition: stm32f4xx.h:645
PVD_IRQn
Definition: stm32f4xx.h:140
CRYP_TypeDef::IV1LR
__IO uint32_t IV1LR
Definition: stm32f4xx.h:959
vsc8
__I int8_t vsc8
Definition: stm32f4xx.h:256
USART6_IRQn
Definition: stm32f4xx.h:210
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition: stm32f4xx.h:414
RTC_TypeDef::TAFCR
__IO uint32_t TAFCR
Definition: stm32f4xx.h:778
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition: stm32f4xx.h:308
DMA1_Stream5_IRQn
Definition: stm32f4xx.h:155
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition: stm32f4xx.h:368
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition: stm32f4xx.h:777
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition: stm32f4xx.h:369
TIM_TypeDef::RESERVED3
uint16_t RESERVED3
Definition: stm32f4xx.h:871
USART_TypeDef::GTPR
__IO uint16_t GTPR
Definition: stm32f4xx.h:920
RCC_TypeDef::AHB1ENR
__IO uint32_t AHB1ENR
Definition: stm32f4xx.h:735
TIM_TypeDef::DIER
__IO uint16_t DIER
Definition: stm32f4xx.h:870
UART4_IRQn
Definition: stm32f4xx.h:191
TIM1_CC_IRQn
Definition: stm32f4xx.h:166
RTC_TypeDef::BKP19R
__IO uint32_t BKP19R
Definition: stm32f4xx.h:801
SPI_TypeDef::RESERVED6
uint16_t RESERVED6
Definition: stm32f4xx.h:851
TIM_TypeDef::RESERVED9
uint16_t RESERVED9
Definition: stm32f4xx.h:884
HASH_TypeDef
HASH.
Definition: stm32f4xx.h:967
DMA1_Stream4_IRQn
Definition: stm32f4xx.h:154
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f4xx.h:906
USART_TypeDef::CR3
__IO uint16_t CR3
Definition: stm32f4xx.h:918
ADC_TypeDef::LTR
__IO uint32_t LTR
Definition: stm32f4xx.h:305
DMA2_Stream0_IRQn
Definition: stm32f4xx.h:195
EXTI2_IRQn
Definition: stm32f4xx.h:147
PWR_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:714
DMA2_Stream3_IRQn
Definition: stm32f4xx.h:198
USART_TypeDef::RESERVED4
uint16_t RESERVED4
Definition: stm32f4xx.h:917
RTC_TypeDef::BKP6R
__IO uint32_t BKP6R
Definition: stm32f4xx.h:788
SPI_TypeDef::CR1
__IO uint16_t CR1
Definition: stm32f4xx.h:838
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition: stm32f4xx.h:434
CRYP_TypeDef::RISR
__IO uint32_t RISR
Definition: stm32f4xx.h:947
uc8
const uint8_t uc8
Definition: stm32f4xx.h:264
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition: stm32f4xx.h:740
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f4xx.h:293
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition: stm32f4xx.h:572
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f4xx.h:661
TIM4_IRQn
Definition: stm32f4xx.h:169
RTC_TypeDef::TSTR
__IO uint32_t TSTR
Definition: stm32f4xx.h:774
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32f4xx.h:298
TIM_TypeDef::RESERVED13
uint16_t RESERVED13
Definition: stm32f4xx.h:897
FLASH_TypeDef
FLASH Registers.
Definition: stm32f4xx.h:570
TIM8_UP_TIM13_IRQn
Definition: stm32f4xx.h:183
TIM_TypeDef::RESERVED8
uint16_t RESERVED8
Definition: stm32f4xx.h:881
TIM8_BRK_TIM12_IRQn
Definition: stm32f4xx.h:182
CRYP_TypeDef::K1LR
__IO uint32_t K1LR
Definition: stm32f4xx.h:951
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition: stm32f4xx.h:776
IRQn_Type
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
RTC_TypeDef::BKP4R
__IO uint32_t BKP4R
Definition: stm32f4xx.h:786
TIM1_BRK_TIM9_IRQn
Definition: stm32f4xx.h:163
ADC_TypeDef::JOFR4
__IO uint32_t JOFR4
Definition: stm32f4xx.h:303
I2C3_ER_IRQn
Definition: stm32f4xx.h:212
SDIO_TypeDef::RESPCMD
__I uint32_t RESPCMD
Definition: stm32f4xx.h:814
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition: stm32f4xx.h:780
I2C_TypeDef::RESERVED7
uint16_t RESERVED7
Definition: stm32f4xx.h:691
TIM_TypeDef::RESERVED14
uint16_t RESERVED14
Definition: stm32f4xx.h:899
SPI2_IRQn
Definition: stm32f4xx.h:175
RCC_TypeDef::AHB2LPENR
__IO uint32_t AHB2LPENR
Definition: stm32f4xx.h:743
I2C_TypeDef::RESERVED6
uint16_t RESERVED6
Definition: stm32f4xx.h:689
IRQn
IRQn
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f4xx.h:127
uc32
const uint32_t uc32
Definition: stm32f4xx.h:262
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:409
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f4xx.h:342
CAN2_RX1_IRQn
Definition: stm32f4xx.h:204
HASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:969
HASH_TypeDef::DIN
__IO uint32_t DIN
Definition: stm32f4xx.h:970
SPI_TypeDef::RESERVED0
uint16_t RESERVED0
Definition: stm32f4xx.h:839
GPIO_TypeDef::OTYPER
__IO uint32_t OTYPER
Definition: stm32f4xx.h:646
DCMI_TypeDef::CWSIZER
__IO uint32_t CWSIZER
Definition: stm32f4xx.h:452
SPI_TypeDef::RESERVED2
uint16_t RESERVED2
Definition: stm32f4xx.h:843
FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4.
Definition: stm32f4xx.h:630
CRC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f4xx.h:396
RTC_TypeDef::BKP3R
__IO uint32_t BKP3R
Definition: stm32f4xx.h:785
EXTI3_IRQn
Definition: stm32f4xx.h:148
MemoryManagement_IRQn
Definition: stm32f4xx.h:131
DCMI_TypeDef::ESCR
__IO uint32_t ESCR
Definition: stm32f4xx.h:449
RCC_TypeDef::SSCGR
__IO uint32_t SSCGR
Definition: stm32f4xx.h:752
I2C_TypeDef::OAR1
__IO uint16_t OAR1
Definition: stm32f4xx.h:680
CRYP_TypeDef::K2LR
__IO uint32_t K2LR
Definition: stm32f4xx.h:953
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f4xx.h:460
USART_TypeDef::BRR
__IO uint16_t BRR
Definition: stm32f4xx.h:912
RTC_TypeDef
Real-Time Clock.
Definition: stm32f4xx.h:760
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f4xx.h:165
TAMP_STAMP_IRQn
Definition: stm32f4xx.h:141
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f4xx.h:407
RNG_TypeDef
HASH.
Definition: stm32f4xx.h:983
I2C_TypeDef::RESERVED2
uint16_t RESERVED2
Definition: stm32f4xx.h:681
USART_TypeDef::RESERVED3
uint16_t RESERVED3
Definition: stm32f4xx.h:915
SDIO_TypeDef::FIFOCNT
__I uint32_t FIFOCNT
Definition: stm32f4xx.h:827
RCC_TypeDef::AHB3RSTR
__IO uint32_t AHB3RSTR
Definition: stm32f4xx.h:730
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition: stm32f4xx.h:383
GPIO_TypeDef::OSPEEDR
__IO uint32_t OSPEEDR
Definition: stm32f4xx.h:647
TIM_TypeDef::EGR
__IO uint16_t EGR
Definition: stm32f4xx.h:874
PWR_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f4xx.h:715
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition: stm32f4xx.h:332
TIM_TypeDef::RESERVED12
uint16_t RESERVED12
Definition: stm32f4xx.h:895
WWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f4xx.h:932
CRYP_TypeDef::IV0LR
__IO uint32_t IV0LR
Definition: stm32f4xx.h:957
EXTI9_5_IRQn
Definition: stm32f4xx.h:162
DCMI_TypeDef::CWSTRTR
__IO uint32_t CWSTRTR
Definition: stm32f4xx.h:451
CAN2_TX_IRQn
Definition: stm32f4xx.h:202
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f4xx.h:750
SDIO_TypeDef
SD host Interface.
Definition: stm32f4xx.h:808
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition: stm32f4xx.h:335
TIM_TypeDef::SR
__IO uint16_t SR
Definition: stm32f4xx.h:872
RTC_WKUP_IRQn
Definition: stm32f4xx.h:142
I2C_TypeDef::OAR2
__IO uint16_t OAR2
Definition: stm32f4xx.h:682
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f4xx.h:184
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition: stm32f4xx.h:573
OTG_HS_WKUP_IRQn
Definition: stm32f4xx.h:215
RTC_TypeDef::CALIBR
__IO uint32_t CALIBR
Definition: stm32f4xx.h:768
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f4xx.h:314
SDIO_TypeDef::DCOUNT
__I uint32_t DCOUNT
Definition: stm32f4xx.h:822
USART_TypeDef::RESERVED0
uint16_t RESERVED0
Definition: stm32f4xx.h:909
TIM_TypeDef::CCMR1
__IO uint16_t CCMR1
Definition: stm32f4xx.h:876
SDIO_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f4xx.h:824
TIM_TypeDef::DCR
__IO uint16_t DCR
Definition: stm32f4xx.h:894
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f4xx.h:836
I2C_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f4xx.h:679
RTC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f4xx.h:765
I2C_TypeDef::RESERVED5
uint16_t RESERVED5
Definition: stm32f4xx.h:687
I2C_TypeDef::CR2
__IO uint16_t CR2
Definition: stm32f4xx.h:678
I2C_TypeDef::TRISE
__IO uint16_t TRISE
Definition: stm32f4xx.h:692
SDIO_TypeDef::DCTRL
__IO uint32_t DCTRL
Definition: stm32f4xx.h:821
DCMI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f4xx.h:444
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition: stm32f4xx.h:584
DMA2_Stream2_IRQn
Definition: stm32f4xx.h:197
EXTI4_IRQn
Definition: stm32f4xx.h:149
vuc8
__I uint8_t vuc8
Definition: stm32f4xx.h:272
TIM_TypeDef::CCER
__IO uint16_t CCER
Definition: stm32f4xx.h:880
SYSCFG_TypeDef::CMPCR
__IO uint32_t CMPCR
Definition: stm32f4xx.h:667
OTG_FS_WKUP_IRQn
Definition: stm32f4xx.h:181
CRYP_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:941
CAN2_RX0_IRQn
Definition: stm32f4xx.h:203
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition: stm32f4xx.h:650
FSMC_Bank4_TypeDef::PIO4
__IO uint32_t PIO4
Definition: stm32f4xx.h:636
CAN1_RX1_IRQn
Definition: stm32f4xx.h:160
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f4xx.h:556
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f4xx.h:429
EXTI_TypeDef::PR
__IO uint32_t PR
Definition: stm32f4xx.h:563
RTC_TypeDef::BKP11R
__IO uint32_t BKP11R
Definition: stm32f4xx.h:793
FSMC_Bank2_TypeDef
Flexible Static Memory Controller Bank2.
Definition: stm32f4xx.h:602
RTC_TypeDef::BKP15R
__IO uint32_t BKP15R
Definition: stm32f4xx.h:797
IWDG_TypeDef::KR
__IO uint32_t KR
Definition: stm32f4xx.h:702
IWDG_TypeDef::PR
__IO uint32_t PR
Definition: stm32f4xx.h:703
WWDG_IRQn
Definition: stm32f4xx.h:139
TIM6_DAC_IRQn
Definition: stm32f4xx.h:193
FSMC_Bank2_TypeDef::PMEM2
__IO uint32_t PMEM2
Definition: stm32f4xx.h:606
RCC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f4xx.h:738
DMA1_Stream1_IRQn
Definition: stm32f4xx.h:151
RCC_TypeDef::AHB2ENR
__IO uint32_t AHB2ENR
Definition: stm32f4xx.h:736
DMA1_Stream2_IRQn
Definition: stm32f4xx.h:152
FSMC_Bank3_TypeDef
Flexible Static Memory Controller Bank3.
Definition: stm32f4xx.h:616
DMA1_Stream0_IRQn
Definition: stm32f4xx.h:150
RCC_TypeDef::AHB3ENR
__IO uint32_t AHB3ENR
Definition: stm32f4xx.h:737
SPI1_IRQn
Definition: stm32f4xx.h:174
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition: stm32f4xx.h:397
RTC_Alarm_IRQn
Definition: stm32f4xx.h:180
TIM_TypeDef::RESERVED0
uint16_t RESERVED0
Definition: stm32f4xx.h:865
ADC_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f4xx.h:297
CAN_TypeDef::IER
__IO uint32_t IER
Definition: stm32f4xx.h:371
TIM_TypeDef::RESERVED4
uint16_t RESERVED4
Definition: stm32f4xx.h:873
FSMC_Bank2_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f4xx.h:608
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32f4xx.h:649
DMA2_Stream4_IRQn
Definition: stm32f4xx.h:199
SPI_TypeDef::CRCPR
__IO uint16_t CRCPR
Definition: stm32f4xx.h:846
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f4xx.h:384
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition: stm32f4xx.h:733
SPI_TypeDef::RESERVED3
uint16_t RESERVED3
Definition: stm32f4xx.h:845
FLASH_IRQn
Definition: stm32f4xx.h:143
RTC_TypeDef::ALRMAR
__IO uint32_t ALRMAR
Definition: stm32f4xx.h:769
RTC_TypeDef::BKP0R
__IO uint32_t BKP0R
Definition: stm32f4xx.h:782
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition: stm32f4xx.h:890
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition: stm32f4xx.h:381
CAN1_RX0_IRQn
Definition: stm32f4xx.h:159
RTC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f4xx.h:763
SPI_TypeDef::CR2
__IO uint16_t CR2
Definition: stm32f4xx.h:840
TIM2_IRQn
Definition: stm32f4xx.h:167
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f4xx.h:643
RCC_TypeDef::APB2LPENR
__IO uint32_t APB2LPENR
Definition: stm32f4xx.h:747
SDIO_TypeDef::POWER
__IO uint32_t POWER
Definition: stm32f4xx.h:810
EXTI_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f4xx.h:558
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32f4xx.h:882
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f4xx.h:399
CRYP_TypeDef::K0LR
__IO uint32_t K0LR
Definition: stm32f4xx.h:949
TIM_TypeDef::BDTR
__IO uint16_t BDTR
Definition: stm32f4xx.h:892
vsc32
__I int32_t vsc32
Definition: stm32f4xx.h:254
RTC_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32f4xx.h:781
RCC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f4xx.h:731
TIM_TypeDef::OR
__IO uint16_t OR
Definition: stm32f4xx.h:898
GPIO_TypeDef::BSRRH
__IO uint16_t BSRRH
Definition: stm32f4xx.h:652
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition: stm32f4xx.h:313
FSMC_Bank4_TypeDef::PATT4
__IO uint32_t PATT4
Definition: stm32f4xx.h:635
vuc16
__I uint16_t vuc16
Definition: stm32f4xx.h:271
I2C_TypeDef::CCR
__IO uint16_t CCR
Definition: stm32f4xx.h:690
I2C2_EV_IRQn
Definition: stm32f4xx.h:172
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32f4xx.h:931
RCC_TypeDef::CIR
__IO uint32_t CIR
Definition: stm32f4xx.h:727
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition: stm32f4xx.h:344
GPIO_TypeDef::PUPDR
__IO uint32_t PUPDR
Definition: stm32f4xx.h:648
DMA_Stream_TypeDef::NDTR
__IO uint32_t NDTR
Definition: stm32f4xx.h:463
DMA_Stream_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32f4xx.h:467
OTG_HS_IRQn
Definition: stm32f4xx.h:216
TIM_TypeDef::RESERVED2
uint16_t RESERVED2
Definition: stm32f4xx.h:869
RNG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:985
I2C3_EV_IRQn
Definition: stm32f4xx.h:211
ETH_TypeDef
Ethernet MAC.
Definition: stm32f4xx.h:482
sc16
const int16_t sc16
Definition: stm32f4xx.h:247
CRYP_TypeDef::DR
__IO uint32_t DR
Definition: stm32f4xx.h:943
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32f4xx.h:410
EXTI0_IRQn
Definition: stm32f4xx.h:145
SPI_TypeDef::RESERVED7
uint16_t RESERVED7
Definition: stm32f4xx.h:853
CRYP_TypeDef::DMACR
__IO uint32_t DMACR
Definition: stm32f4xx.h:945
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32f4xx.h:309
SDIO_TypeDef::ARG
__IO uint32_t ARG
Definition: stm32f4xx.h:812
ADC_TypeDef::JOFR3
__IO uint32_t JOFR3
Definition: stm32f4xx.h:302
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition: stm32f4xx.h:333
DCMI_TypeDef
DCMI.
Definition: stm32f4xx.h:441
DCMI_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32f4xx.h:447
TIM_TypeDef::CCMR2
__IO uint16_t CCMR2
Definition: stm32f4xx.h:878
DMA2_Stream5_IRQn
Definition: stm32f4xx.h:207
CRYP_TypeDef::IMSCR
__IO uint32_t IMSCR
Definition: stm32f4xx.h:946
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition: stm32f4xx.h:749
SDIO_TypeDef::MASK
__IO uint32_t MASK
Definition: stm32f4xx.h:825
RTC_TypeDef::PRER
__IO uint32_t PRER
Definition: stm32f4xx.h:766
EXTI_TypeDef::SWIER
__IO uint32_t SWIER
Definition: stm32f4xx.h:562
FSMC_Bank4_TypeDef::SR4
__IO uint32_t SR4
Definition: stm32f4xx.h:633
TIM7_IRQn
Definition: stm32f4xx.h:194
CRYP_TypeDef::IV1RR
__IO uint32_t IV1RR
Definition: stm32f4xx.h:960
FSMC_Bank4_TypeDef::PMEM4
__IO uint32_t PMEM4
Definition: stm32f4xx.h:634
TIM1_UP_TIM10_IRQn
Definition: stm32f4xx.h:164
I2C1_EV_IRQn
Definition: stm32f4xx.h:170
DCMI_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f4xx.h:448
RTC_TypeDef::BKP12R
__IO uint32_t BKP12R
Definition: stm32f4xx.h:794
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32f4xx.h:310
OTG_FS_IRQn
Definition: stm32f4xx.h:206
RCC_TypeDef::AHB1LPENR
__IO uint32_t AHB1LPENR
Definition: stm32f4xx.h:742
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition: stm32f4xx.h:398
TIM_TypeDef::RESERVED11
uint16_t RESERVED11
Definition: stm32f4xx.h:893
SDIO_TypeDef::RESP3
__I uint32_t RESP3
Definition: stm32f4xx.h:817
ADC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f4xx.h:295
CRYP_TypeDef
Crypto Processor.
Definition: stm32f4xx.h:939
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f4xx.h:700
IWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f4xx.h:705
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f4xx.h:928
RTC_TypeDef::BKP1R
__IO uint32_t BKP1R
Definition: stm32f4xx.h:783
RCC_TypeDef::APB1RSTR
__IO uint32_t APB1RSTR
Definition: stm32f4xx.h:732
RTC_TypeDef::ALRMBR
__IO uint32_t ALRMBR
Definition: stm32f4xx.h:770
RCC_TypeDef::PLLCFGR
__IO uint32_t PLLCFGR
Definition: stm32f4xx.h:725
sc8
const int8_t sc8
Definition: stm32f4xx.h:248
FSMC_Bank3_TypeDef::PATT3
__IO uint32_t PATT3
Definition: stm32f4xx.h:621
TIM_TypeDef::CR1
__IO uint16_t CR1
Definition: stm32f4xx.h:864
I2C_TypeDef::DR
__IO uint16_t DR
Definition: stm32f4xx.h:684
FPU_IRQn
Definition: stm32f4xx.h:220
SDIO_TypeDef::STA
__I uint32_t STA
Definition: stm32f4xx.h:823
SPI_TypeDef::I2SPR
__IO uint16_t I2SPR
Definition: stm32f4xx.h:854
RTC_TypeDef::BKP10R
__IO uint32_t BKP10R
Definition: stm32f4xx.h:792
USART_TypeDef::RESERVED2
uint16_t RESERVED2
Definition: stm32f4xx.h:913
TIM_TypeDef::CR2
__IO uint16_t CR2
Definition: stm32f4xx.h:866
RTC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:764
TIM_TypeDef::RCR
__IO uint16_t RCR
Definition: stm32f4xx.h:886
DMA_Stream_TypeDef::M0AR
__IO uint32_t M0AR
Definition: stm32f4xx.h:465
USART3_IRQn
Definition: stm32f4xx.h:178
USART_TypeDef::RESERVED5
uint16_t RESERVED5
Definition: stm32f4xx.h:919
TIM_TypeDef::RESERVED6
uint16_t RESERVED6
Definition: stm32f4xx.h:877
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition: stm32f4xx.h:378
DebugMonitor_IRQn
Definition: stm32f4xx.h:135
uc16
const uint16_t uc16
Definition: stm32f4xx.h:263
RNG_TypeDef::DR
__IO uint32_t DR
Definition: stm32f4xx.h:987
SDIO_TypeDef::CLKCR
__IO uint32_t CLKCR
Definition: stm32f4xx.h:811
TIM_TypeDef::DMAR
__IO uint16_t DMAR
Definition: stm32f4xx.h:896
ADC_IRQn
Definition: stm32f4xx.h:157
RTC_TypeDef::BKP13R
__IO uint32_t BKP13R
Definition: stm32f4xx.h:795
SDIO_TypeDef::RESP2
__I uint32_t RESP2
Definition: stm32f4xx.h:816
ADC_TypeDef::JOFR1
__IO uint32_t JOFR1
Definition: stm32f4xx.h:300
s32
int32_t s32
Definition: stm32f4xx.h:242
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition: stm32f4xx.h:431
I2C_TypeDef::RESERVED4
uint16_t RESERVED4
Definition: stm32f4xx.h:685
TIM_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f4xx.h:867
ADC_TypeDef::HTR
__IO uint32_t HTR
Definition: stm32f4xx.h:304
SPI_TypeDef::RXCRCR
__IO uint16_t RXCRCR
Definition: stm32f4xx.h:848
BusFault_IRQn
Definition: stm32f4xx.h:132
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition: stm32f4xx.h:347
DMA1_Stream6_IRQn
Definition: stm32f4xx.h:156
SPI_TypeDef::SR
__IO uint16_t SR
Definition: stm32f4xx.h:842
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32f4xx.h:418
DMA2_Stream1_IRQn
Definition: stm32f4xx.h:196
I2C_TypeDef::RESERVED0
uint16_t RESERVED0
Definition: stm32f4xx.h:677
DMA_Stream_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:462
SPI3_IRQn
Definition: stm32f4xx.h:190
PendSV_IRQn
Definition: stm32f4xx.h:136
TIM_TypeDef
TIM.
Definition: stm32f4xx.h:862
DMA2_Stream7_IRQn
Definition: stm32f4xx.h:209
RTC_TypeDef::BKP9R
__IO uint32_t BKP9R
Definition: stm32f4xx.h:791
GPIO_TypeDef::BSRRL
__IO uint16_t BSRRL
Definition: stm32f4xx.h:651
RCC_TypeDef::AHB1RSTR
__IO uint32_t AHB1RSTR
Definition: stm32f4xx.h:728
SPI_TypeDef::DR
__IO uint16_t DR
Definition: stm32f4xx.h:844
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition: stm32f4xx.h:779
CRYP_TypeDef::SR
__IO uint32_t SR
Definition: stm32f4xx.h:942
ETH_IRQn
Definition: stm32f4xx.h:200
DMA1_Stream7_IRQn
Definition: stm32f4xx.h:186
RCC_TypeDef::AHB3LPENR
__IO uint32_t AHB3LPENR
Definition: stm32f4xx.h:744
SDIO_TypeDef::RESP4
__I uint32_t RESP4
Definition: stm32f4xx.h:818
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f4xx.h:354
CRYP_TypeDef::K2RR
__IO uint32_t K2RR
Definition: stm32f4xx.h:954
RTC_TypeDef::BKP8R
__IO uint32_t BKP8R
Definition: stm32f4xx.h:790
ETH_WKUP_IRQn
Definition: stm32f4xx.h:201
TIM8_CC_IRQn
Definition: stm32f4xx.h:185
USART_TypeDef::SR
__IO uint16_t SR
Definition: stm32f4xx.h:908
PWR_TypeDef
Power Control.
Definition: stm32f4xx.h:712
FSMC_Bank3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f4xx.h:622
FSMC_Bank3_TypeDef::SR3
__IO uint32_t SR3
Definition: stm32f4xx.h:619
CAN1_SCE_IRQn
Definition: stm32f4xx.h:161
FSMC_Bank2_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32f4xx.h:605
CRYP_TypeDef::K1RR
__IO uint32_t K1RR
Definition: stm32f4xx.h:952
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition: stm32f4xx.h:415
UsageFault_IRQn
Definition: stm32f4xx.h:133
TIM_TypeDef::SMCR
__IO uint16_t SMCR
Definition: stm32f4xx.h:868
TIM_TypeDef::RESERVED5
uint16_t RESERVED5
Definition: stm32f4xx.h:875
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f4xx.h:722
FSMC_Bank2_TypeDef::PCR2
__IO uint32_t PCR2
Definition: stm32f4xx.h:604
RTC_TypeDef::WPR
__IO uint32_t WPR
Definition: stm32f4xx.h:771
HASH_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f4xx.h:973
FSMC_Bank2_TypeDef::PATT2
__IO uint32_t PATT2
Definition: stm32f4xx.h:607
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32f4xx.h:889
FSMC_IRQn
Definition: stm32f4xx.h:187
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f4xx.h:726
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition: stm32f4xx.h:416
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition: stm32f4xx.h:379
HASH_RNG_IRQn
Definition: stm32f4xx.h:219
RCC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:724
RTC_TypeDef::BKP17R
__IO uint32_t BKP17R
Definition: stm32f4xx.h:799
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition: stm32f4xx.h:367
CAN_TypeDef
Controller Area Network.
Definition: stm32f4xx.h:364
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32f4xx.h:419
CRYP_TypeDef::K0RR
__IO uint32_t K0RR
Definition: stm32f4xx.h:950
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:432
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition: stm32f4xx.h:345
SYSCFG_TypeDef::PMC
__IO uint32_t PMC
Definition: stm32f4xx.h:664
I2C2_ER_IRQn
Definition: stm32f4xx.h:173
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition: stm32f4xx.h:357
CRYP_TypeDef::DOUT
__IO uint32_t DOUT
Definition: stm32f4xx.h:944
CRYP_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32f4xx.h:948
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition: stm32f4xx.h:704
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition: stm32f4xx.h:891
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition: stm32f4xx.h:653
USART_TypeDef::CR1
__IO uint16_t CR1
Definition: stm32f4xx.h:914
SDIO_TypeDef::DTIMER
__IO uint32_t DTIMER
Definition: stm32f4xx.h:819
RCC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f4xx.h:745
TIM_TypeDef::RESERVED10
uint16_t RESERVED10
Definition: stm32f4xx.h:887
SDIO_IRQn
Definition: stm32f4xx.h:188
OTG_HS_EP1_IN_IRQn
Definition: stm32f4xx.h:214
RCC_IRQn
Definition: stm32f4xx.h:144
I2C_TypeDef::CR1
__IO uint16_t CR1
Definition: stm32f4xx.h:676
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32f4xx.h:411
CRYP_TypeDef::K3LR
__IO uint32_t K3LR
Definition: stm32f4xx.h:955
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32f4xx.h:366
FSMC_Bank3_TypeDef::PMEM3
__IO uint32_t PMEM3
Definition: stm32f4xx.h:620
SDIO_TypeDef::DLEN
__IO uint32_t DLEN
Definition: stm32f4xx.h:820
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition: stm32f4xx.h:370
RTC_TypeDef::BKP7R
__IO uint32_t BKP7R
Definition: stm32f4xx.h:789
RTC_TypeDef::TSDR
__IO uint32_t TSDR
Definition: stm32f4xx.h:775
RNG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f4xx.h:986
I2C_TypeDef::RESERVED8
uint16_t RESERVED8
Definition: stm32f4xx.h:693
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f4xx.h:674
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition: stm32f4xx.h:413
EXTI1_IRQn
Definition: stm32f4xx.h:146
EXTI_TypeDef::RTSR
__IO uint32_t RTSR
Definition: stm32f4xx.h:560
RCC_TypeDef::PLLI2SCFGR
__IO uint32_t PLLI2SCFGR
Definition: stm32f4xx.h:753
DBGMCU_TypeDef::APB1FZ
__IO uint32_t APB1FZ
Definition: stm32f4xx.h:433
USART_TypeDef::CR2
__IO uint16_t CR2
Definition: stm32f4xx.h:916
USART2_IRQn
Definition: stm32f4xx.h:177
SDIO_TypeDef::CMD
__IO uint32_t CMD
Definition: stm32f4xx.h:813
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition: stm32f4xx.h:312
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition: stm32f4xx.h:372
CRYP_TypeDef::K3RR
__IO uint32_t K3RR
Definition: stm32f4xx.h:956
DMA_Stream_TypeDef::PAR
__IO uint32_t PAR
Definition: stm32f4xx.h:464
ADC_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f4xx.h:296
I2C_TypeDef::SR2
__IO uint16_t SR2
Definition: stm32f4xx.h:688
DCMI_IRQn
Definition: stm32f4xx.h:217
vuc32
__I uint32_t vuc32
Definition: stm32f4xx.h:270
SYSCFG_TypeDef::MEMRMP
__IO uint32_t MEMRMP
Definition: stm32f4xx.h:663
RCC_TypeDef::APB1ENR
__IO uint32_t APB1ENR
Definition: stm32f4xx.h:739
CAN1_TX_IRQn
Definition: stm32f4xx.h:158
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition: stm32f4xx.h:385
I2C_TypeDef::SR1
__IO uint16_t SR1
Definition: stm32f4xx.h:686
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition: stm32f4xx.h:307
FSMC_Bank4_TypeDef::PCR4
__IO uint32_t PCR4
Definition: stm32f4xx.h:632
CRYP_IRQn
Definition: stm32f4xx.h:218
WWDG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:930
TIM_TypeDef::RESERVED7
uint16_t RESERVED7
Definition: stm32f4xx.h:879
DCMI_TypeDef::ESUR
__IO uint32_t ESUR
Definition: stm32f4xx.h:450
DCMI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f4xx.h:453
TIM_TypeDef::PSC
__IO uint16_t PSC
Definition: stm32f4xx.h:883
vsc16
__I int16_t vsc16
Definition: stm32f4xx.h:255
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition: stm32f4xx.h:373
DMA2_Stream6_IRQn
Definition: stm32f4xx.h:208
I2C_TypeDef::RESERVED3
uint16_t RESERVED3
Definition: stm32f4xx.h:683
SPI_TypeDef::I2SCFGR
__IO uint16_t I2SCFGR
Definition: stm32f4xx.h:852
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:400
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32f4xx.h:417
RTC_TypeDef::BKP18R
__IO uint32_t BKP18R
Definition: stm32f4xx.h:800
USART_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f4xx.h:911
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition: stm32f4xx.h:421
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition: stm32f4xx.h:334
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f4xx.h:380
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition: stm32f4xx.h:412
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition: stm32f4xx.h:574
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition: stm32f4xx.h:773
EXTI15_10_IRQn
Definition: stm32f4xx.h:179
DMA_Stream_TypeDef::M1AR
__IO uint32_t M1AR
Definition: stm32f4xx.h:466
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition: stm32f4xx.h:593
TIM3_IRQn
Definition: stm32f4xx.h:168
RTC_TypeDef::BKP5R
__IO uint32_t BKP5R
Definition: stm32f4xx.h:787
CAN2_SCE_IRQn
Definition: stm32f4xx.h:205
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition: stm32f4xx.h:299
CRYP_TypeDef::IV0RR
__IO uint32_t IV0RR
Definition: stm32f4xx.h:958
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition: stm32f4xx.h:356
SPI_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f4xx.h:841
RCC_TypeDef::APB1LPENR
__IO uint32_t APB1LPENR
Definition: stm32f4xx.h:746
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32f4xx.h:420
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32f4xx.h:888
FSMC_Bank2_TypeDef::ECCR2
__IO uint32_t ECCR2
Definition: stm32f4xx.h:609
DCMI_TypeDef::RISR
__IO uint32_t RISR
Definition: stm32f4xx.h:445
EXTI_TypeDef::FTSR
__IO uint32_t FTSR
Definition: stm32f4xx.h:561
FLASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:576
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f4xx.h:330
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
UART5_IRQn
Definition: stm32f4xx.h:192
SPI_TypeDef::RESERVED4
uint16_t RESERVED4
Definition: stm32f4xx.h:847
sc32
const int32_t sc32
Definition: stm32f4xx.h:246
RTC_TypeDef::BKP2R
__IO uint32_t BKP2R
Definition: stm32f4xx.h:784
USART1_IRQn
Definition: stm32f4xx.h:176
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32f4xx.h:306
EXTI_TypeDef::EMR
__IO uint32_t EMR
Definition: stm32f4xx.h:559
FSMC_Bank3_TypeDef::ECCR3
__IO uint32_t ECCR3
Definition: stm32f4xx.h:623
USART_TypeDef::RESERVED6
uint16_t RESERVED6
Definition: stm32f4xx.h:921
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32f4xx.h:885
I2C1_ER_IRQn
Definition: stm32f4xx.h:171
RTC_TypeDef::BKP14R
__IO uint32_t BKP14R
Definition: stm32f4xx.h:796
SPI_TypeDef::TXCRCR
__IO uint16_t TXCRCR
Definition: stm32f4xx.h:850
FSMC_Bank3_TypeDef::PCR3
__IO uint32_t PCR3
Definition: stm32f4xx.h:618
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