RCC_TypeDef Struct Reference

Reset and Clock Control. More...

#include "C:/Programs/ARMEBS4/current/doc/eclipse-doc/ext/libheivs_stm32/include/stm32/stm32f4xx.h"

Collaboration diagram for RCC_TypeDef:

Data Fields
__IO uint32_t	CR
__IO uint32_t	PLLCFGR
__IO uint32_t	CFGR
__IO uint32_t	CIR
__IO uint32_t	AHB1RSTR
__IO uint32_t	AHB2RSTR
__IO uint32_t	AHB3RSTR
uint32_t	RESERVED0
__IO uint32_t	APB1RSTR
__IO uint32_t	APB2RSTR
uint32_t	RESERVED1 [2]
__IO uint32_t	AHB1ENR
__IO uint32_t	AHB2ENR
__IO uint32_t	AHB3ENR
uint32_t	RESERVED2
__IO uint32_t	APB1ENR
__IO uint32_t	APB2ENR
uint32_t	RESERVED3 [2]
__IO uint32_t	AHB1LPENR
__IO uint32_t	AHB2LPENR
__IO uint32_t	AHB3LPENR
uint32_t	RESERVED4
__IO uint32_t	APB1LPENR
__IO uint32_t	APB2LPENR
uint32_t	RESERVED5 [2]
__IO uint32_t	BDCR
__IO uint32_t	CSR
uint32_t	RESERVED6 [2]
__IO uint32_t	SSCGR
__IO uint32_t	PLLI2SCFGR

Detailed Description

Reset and Clock Control.

Definition at line 722 of file stm32f4xx.h.

Field Documentation

__IO uint32_t RCC_TypeDef::CR

RCC clock control register, Address offset: 0x00

Definition at line 724 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::PLLCFGR

RCC PLL configuration register, Address offset: 0x04

Definition at line 725 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::CFGR

RCC clock configuration register, Address offset: 0x08

Definition at line 726 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::CIR

RCC clock interrupt register, Address offset: 0x0C

Definition at line 727 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::AHB1RSTR

RCC AHB1 peripheral reset register, Address offset: 0x10

Definition at line 728 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::AHB2RSTR

RCC AHB2 peripheral reset register, Address offset: 0x14

Definition at line 729 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::AHB3RSTR

RCC AHB3 peripheral reset register, Address offset: 0x18

Definition at line 730 of file stm32f4xx.h.

uint32_t RCC_TypeDef::RESERVED0

Reserved, 0x1C

Definition at line 731 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::APB1RSTR

RCC APB1 peripheral reset register, Address offset: 0x20

Definition at line 732 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::APB2RSTR

RCC APB2 peripheral reset register, Address offset: 0x24

Definition at line 733 of file stm32f4xx.h.

uint32_t RCC_TypeDef::RESERVED1[2]

Reserved, 0x28-0x2C

Definition at line 734 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::AHB1ENR

RCC AHB1 peripheral clock register, Address offset: 0x30

Definition at line 735 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::AHB2ENR

RCC AHB2 peripheral clock register, Address offset: 0x34

Definition at line 736 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::AHB3ENR

RCC AHB3 peripheral clock register, Address offset: 0x38

Definition at line 737 of file stm32f4xx.h.

uint32_t RCC_TypeDef::RESERVED2

Reserved, 0x3C

Definition at line 738 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::APB1ENR

RCC APB1 peripheral clock enable register, Address offset: 0x40

Definition at line 739 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::APB2ENR

RCC APB2 peripheral clock enable register, Address offset: 0x44

Definition at line 740 of file stm32f4xx.h.

uint32_t RCC_TypeDef::RESERVED3[2]

Reserved, 0x48-0x4C

Definition at line 741 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::AHB1LPENR

RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50

Definition at line 742 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::AHB2LPENR

RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54

Definition at line 743 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::AHB3LPENR

RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58

Definition at line 744 of file stm32f4xx.h.

uint32_t RCC_TypeDef::RESERVED4

Reserved, 0x5C

Definition at line 745 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::APB1LPENR

RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60

Definition at line 746 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::APB2LPENR

RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64

Definition at line 747 of file stm32f4xx.h.

uint32_t RCC_TypeDef::RESERVED5[2]

Reserved, 0x68-0x6C

Definition at line 748 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::BDCR

RCC Backup domain control register, Address offset: 0x70

Definition at line 749 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::CSR

RCC clock control & status register, Address offset: 0x74

Definition at line 750 of file stm32f4xx.h.

uint32_t RCC_TypeDef::RESERVED6[2]

Reserved, 0x78-0x7C

Definition at line 751 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::SSCGR

RCC spread spectrum clock generation register, Address offset: 0x80

Definition at line 752 of file stm32f4xx.h.

__IO uint32_t RCC_TypeDef::PLLI2SCFGR

RCC PLLI2S configuration register, Address offset: 0x84

Definition at line 753 of file stm32f4xx.h.