ARMEBS4  revision-26.06.2015
Data Fields
FSMC_NORSRAMTimingInitTypeDef Struct Reference

Timing parameters For NOR/SRAM Banks. More...

#include "C:/Programs/ARMEBS4/current/doc/eclipse-doc/ext/libheivs_stm32/include/stm32/stm32f4xx_fsmc.h"

Collaboration diagram for FSMC_NORSRAMTimingInitTypeDef:
Collaboration graph

Data Fields

uint32_t FSMC_AddressSetupTime
 
uint32_t FSMC_AddressHoldTime
 
uint32_t FSMC_DataSetupTime
 
uint32_t FSMC_BusTurnAroundDuration
 
uint32_t FSMC_CLKDivision
 
uint32_t FSMC_DataLatency
 
uint32_t FSMC_AccessMode
 

Detailed Description

Timing parameters For NOR/SRAM Banks.

Definition at line 47 of file stm32f4xx_fsmc.h.

Field Documentation

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime

Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between 0 and 0xF.

Note
This parameter is not used with synchronous NOR Flash memories.

Definition at line 49 of file stm32f4xx_fsmc.h.

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime

Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between 0 and 0xF.

Note
This parameter is not used with synchronous NOR Flash memories.

Definition at line 54 of file stm32f4xx_fsmc.h.

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime

Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between 0 and 0xFF.

Note
This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories.

Definition at line 59 of file stm32f4xx_fsmc.h.

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration

Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between 0 and 0xF.

Note
This parameter is only used for multiplexed NOR Flash memories.

Definition at line 64 of file stm32f4xx_fsmc.h.

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision

Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between 1 and 0xF.

Note
This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses.

Definition at line 69 of file stm32f4xx_fsmc.h.

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency

Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below:

  • It must be set to 0 in case of a CRAM
  • It is don't care in asynchronous NOR, SRAM or ROM accesses
  • It may assume a value between 0 and 0xF in NOR Flash memories with synchronous burst mode enable

Definition at line 73 of file stm32f4xx_fsmc.h.

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode

Specifies the asynchronous access mode. This parameter can be a value of FSMC_Access_Mode

Definition at line 81 of file stm32f4xx_fsmc.h.