DMA_Rx_descriptor

Collaboration diagram for DMA_Rx_descriptor:

Macros
#define	ETH_DMARxDesc_OWN
	Bit definition of RDES0 register: DMA Rx descriptor status register. More...
#define	ETH_DMARxDesc_AFM
#define	ETH_DMARxDesc_FL
#define	ETH_DMARxDesc_ES
#define	ETH_DMARxDesc_DE
#define	ETH_DMARxDesc_SAF
#define	ETH_DMARxDesc_LE
#define	ETH_DMARxDesc_OE
#define	ETH_DMARxDesc_VLAN
#define	ETH_DMARxDesc_FS
#define	ETH_DMARxDesc_LS
#define	ETH_DMARxDesc_IPV4HCE
#define	ETH_DMARxDesc_LC
#define	ETH_DMARxDesc_FT
#define	ETH_DMARxDesc_RWT
#define	ETH_DMARxDesc_RE
#define	ETH_DMARxDesc_DBE
#define	ETH_DMARxDesc_CE
#define	ETH_DMARxDesc_MAMPCE
#define	ETH_DMARxDesc_DIC
	Bit definition of RDES1 register. More...
#define	ETH_DMARxDesc_RBS2
#define	ETH_DMARxDesc_RER
#define	ETH_DMARxDesc_RCH
#define	ETH_DMARxDesc_RBS1
#define	ETH_DMARxDesc_B1AP
	Bit definition of RDES2 register. More...
#define	ETH_DMARxDesc_B2AP
	Bit definition of RDES3 register. More...

Detailed Description

Macro Definition Documentation

#define ETH_DMARxDesc_OWN

Bit definition of RDES0 register: DMA Rx descriptor status register.

DMA Rx Descriptor
--------------------------------------------------------------------------------------------------------------------
RDES0 | OWN(31) |                                             Status [30:0]                                          |
---------------------------------------------------------------------------------------------------------------------
RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
---------------------------------------------------------------------------------------------------------------------
RDES2 |                                       Buffer1 Address [31:0]                                                 |
---------------------------------------------------------------------------------------------------------------------
RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |
---------------------------------------------------------------------------------------------------------------------

OWN bit: descriptor is owned by DMA engine

Definition at line 446 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_AFM

DA Filter Fail for the rx frame

Definition at line 447 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_FL

Receive descriptor frame length

Definition at line 448 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_ES

Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE

Definition at line 449 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_DE

Descriptor error: no more descriptors for receive frame

Definition at line 450 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_SAF

SA Filter Fail for the received frame

Definition at line 451 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_LE

Frame size not matching with length field

Definition at line 452 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_OE

Overflow Error: Frame was damaged due to buffer overflow

Definition at line 453 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_VLAN

VLAN Tag: received frame is a VLAN frame

Definition at line 454 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_FS

First descriptor of the frame

Definition at line 455 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_LS

Last descriptor of the frame

Definition at line 456 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_IPV4HCE

IPC Checksum Error: Rx Ipv4 header checksum error

Definition at line 457 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_LC

Late collision occurred during reception

Definition at line 458 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_FT

Frame type - Ethernet, otherwise 802.3

Definition at line 459 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_RWT

Receive Watchdog Timeout: watchdog timer expired during reception

Definition at line 460 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_RE

Receive error: error reported by MII interface

Definition at line 461 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_DBE

Dribble bit error: frame contains non int multiple of 8 bits

Definition at line 462 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_CE

CRC error

Definition at line 463 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_MAMPCE

Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error

Definition at line 464 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_DIC

Bit definition of RDES1 register.

Disable Interrupt on Completion

Definition at line 469 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_RBS2

Receive Buffer2 Size

Definition at line 470 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_RER

Receive End of Ring

Definition at line 471 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_RCH

Second Address Chained

Definition at line 472 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_RBS1

Receive Buffer1 Size

Definition at line 473 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_B1AP

Bit definition of RDES2 register.

Buffer1 Address Pointer

Definition at line 478 of file stm32f4xx_eth.h.

#define ETH_DMARxDesc_B2AP

Bit definition of RDES3 register.

Buffer2 Address Pointer

Definition at line 483 of file stm32f4xx_eth.h.