ARMEBS4  revision-26.06.2015
stm32f4xx_eth.h
1 /**
2  ******************************************************************************
3  * @file stm32f4x7_eth.h
4  * @author MCD Application Team
5  * @version V1.1.0
6  * @date 31-July-2013
7  * @brief This file contains all the functions prototypes for the Ethernet
8  * firmware driver.
9  ******************************************************************************
10  * @attention
11  *
12  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
13  *
14  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15  * You may not use this file except in compliance with the License.
16  * You may obtain a copy of the License at:
17  *
18  * http://www.st.com/software_license_agreement_liberty_v2
19  *
20  * Unless required by applicable law or agreed to in writing, software
21  * distributed under the License is distributed on an "AS IS" BASIS,
22  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23  * See the License for the specific language governing permissions and
24  * limitations under the License.
25  *
26  ******************************************************************************
27  */
28 
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F4x7_ETH_H
31 #define __STM32F4x7_ETH_H
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /* Includes ------------------------------------------------------------------*/
38 //#include "config/lwip_opt.h"
39 #include "stm32/stm32f4xx.h"
40 
41 #include <stdint.h>
42 /** @addtogroup STM32F4x7_ETH_Driver
43  * @{
44  */
45 
46 /** @defgroup ETH_Exported_Types
47  * @{
48  */
49 
50 /**
51  * @brief ETH MAC Init structure definition
52  * @note The user should not configure all the ETH_InitTypeDef structure's fields.
53  * By calling the ETH_StructInit function the structure�s fields are set to their default values.
54  * Only the parameters that will be set to a non-default value should be configured.
55  */
56 typedef struct {
57 /**
58  * @brief / * MAC
59  */
60  uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
61  The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
62  and the mode (half/full-duplex).
63  This parameter can be a value of @ref ETH_AutoNegotiation */
64 
65  uint32_t ETH_Watchdog; /*!< Selects or not the Watchdog timer
66  When enabled, the MAC allows no more then 2048 bytes to be received.
67  When disabled, the MAC can receive up to 16384 bytes.
68  This parameter can be a value of @ref ETH_watchdog */
69 
70  uint32_t ETH_Jabber; /*!< Selects or not Jabber timer
71  When enabled, the MAC allows no more then 2048 bytes to be sent.
72  When disabled, the MAC can send up to 16384 bytes.
73  This parameter can be a value of @ref ETH_Jabber */
74 
75  uint32_t ETH_InterFrameGap; /*!< Selects the minimum IFG between frames during transmission
76  This parameter can be a value of @ref ETH_Inter_Frame_Gap */
77 
78  uint32_t ETH_CarrierSense; /*!< Selects or not the Carrier Sense
79  This parameter can be a value of @ref ETH_Carrier_Sense */
80 
81  uint32_t ETH_Speed; /*!< Sets the Ethernet speed: 10/100 Mbps
82  This parameter can be a value of @ref ETH_Speed */
83 
84  uint32_t ETH_ReceiveOwn; /*!< Selects or not the ReceiveOwn
85  ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
86  in Half-Duplex mode
87  This parameter can be a value of @ref ETH_Receive_Own */
88 
89  uint32_t ETH_LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode
90  This parameter can be a value of @ref ETH_Loop_Back_Mode */
91 
92  uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
93  This parameter can be a value of @ref ETH_Duplex_Mode */
94 
95  uint32_t ETH_ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
96  This parameter can be a value of @ref ETH_Checksum_Offload */
97 
98  uint32_t ETH_RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
99  when a collision occurs (Half-Duplex mode)
100  This parameter can be a value of @ref ETH_Retry_Transmission */
101 
102  uint32_t ETH_AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping
103  This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
104 
105  uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value
106  This parameter can be a value of @ref ETH_Back_Off_Limit */
107 
108  uint32_t ETH_DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode)
109  This parameter can be a value of @ref ETH_Deferral_Check */
110 
111  uint32_t ETH_ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering)
112  This parameter can be a value of @ref ETH_Receive_All */
113 
114  uint32_t ETH_SourceAddrFilter; /*!< Selects the Source Address Filter mode
115  This parameter can be a value of @ref ETH_Source_Addr_Filter */
116 
117  uint32_t ETH_PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
118  This parameter can be a value of @ref ETH_Pass_Control_Frames */
119 
120  uint32_t ETH_BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames
121  This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
122 
123  uint32_t ETH_DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames
124  This parameter can be a value of @ref ETH_Destination_Addr_Filter */
125 
126  uint32_t ETH_PromiscuousMode; /*!< Selects or not the Promiscuous Mode
127  This parameter can be a value of @ref ETH_Promiscuous_Mode */
128 
129  uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
130  This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
131 
132  uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
133  This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
134 
135  uint32_t ETH_HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */
136 
137  uint32_t ETH_HashTableLow; /*!< This field holds the lower 32 bits of Hash table. */
138 
139  uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the
140  transmit control frame */
141 
142  uint32_t ETH_ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames
143  This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
144 
145  uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
146  automatic retransmission of PAUSE Frame
147  This parameter can be a value of @ref ETH_Pause_Low_Threshold */
148 
149  uint32_t ETH_UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
150  unicast address and unique multicast address)
151  This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
152 
153  uint32_t ETH_ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
154  disable its transmitter for a specified time (Pause Time)
155  This parameter can be a value of @ref ETH_Receive_Flow_Control */
156 
157  uint32_t ETH_TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
158  or the MAC back-pressure operation (Half-Duplex mode)
159  This parameter can be a value of @ref ETH_Transmit_Flow_Control */
160 
161  uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
162  comparison and filtering
163  This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
164 
165  uint32_t ETH_VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
166 
167 /**
168  * @brief / * DMA
169  */
170 
171  uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames
172  This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
173 
174  uint32_t ETH_ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode
175  This parameter can be a value of @ref ETH_Receive_Store_Forward */
176 
177  uint32_t ETH_FlushReceivedFrame; /*!< Enables or disables the flushing of received frames
178  This parameter can be a value of @ref ETH_Flush_Received_Frame */
179 
180  uint32_t ETH_TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode
181  This parameter can be a value of @ref ETH_Transmit_Store_Forward */
182 
183  uint32_t ETH_TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control
184  This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
185 
186  uint32_t ETH_ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames
187  This parameter can be a value of @ref ETH_Forward_Error_Frames */
188 
189  uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
190  and length less than 64 bytes) including pad-bytes and CRC)
191  This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
192 
193  uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO
194  This parameter can be a value of @ref ETH_Receive_Threshold_Control */
195 
196  uint32_t ETH_SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
197  frame of Transmit data even before obtaining the status for the first frame.
198  This parameter can be a value of @ref ETH_Second_Frame_Operate */
199 
200  uint32_t ETH_AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats
201  This parameter can be a value of @ref ETH_Address_Aligned_Beats */
202 
203  uint32_t ETH_FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers
204  This parameter can be a value of @ref ETH_Fixed_Burst */
205 
206  uint32_t ETH_RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction
207  This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
208 
209  uint32_t ETH_TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction
210  This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
211 
212  uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */
213 
214  uint32_t ETH_DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration
215  This parameter can be a value of @ref ETH_DMA_Arbitration */
216 }ETH_InitTypeDef;
217 
218 /**--------------------------------------------------------------------------**/
219 /**
220  * @brief DMA descriptors types
221  */
222 /**--------------------------------------------------------------------------**/
223 
224 /**
225  * @brief ETH DMA Descriptors data structure definition
226  */
227 typedef struct {
228  __IO uint32_t Status; /*!< Status */
229  uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
230  uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
231  uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
232 /* Enhanced ETHERNET DMA PTP Descriptors */
233 #ifdef USE_ENHANCED_DMA_DESCRIPTORS
234  uint32_t ExtendedStatus; /* Extended status for PTP receive descriptor */
235  uint32_t Reserved1; /* Reserved */
236  uint32_t TimeStampLow; /* Time Stamp Low value for transmit and receive */
237  uint32_t TimeStampHigh; /* Time Stamp High value for transmit and receive */
238 #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
239 } ETH_DMADESCTypeDef;
240 
241 
242 typedef struct{
243  u32 length;
244  u32 buffer;
245  __IO ETH_DMADESCTypeDef *descriptor;
246 }FrameTypeDef;
247 
248 
249 typedef struct {
250  __IO ETH_DMADESCTypeDef *FS_Rx_Desc; /*!< First Segment Rx Desc */
251  __IO ETH_DMADESCTypeDef *LS_Rx_Desc; /*!< Last Segment Rx Desc */
252  __IO uint32_t Seg_Count; /*!< Segment count */
253 } ETH_DMA_Rx_Frame_infos;
254 
255 
256 /**
257  * @}
258  */
259 
260 /** @defgroup ETH_Exported_Constants
261  * @{
262  */
263 
264 /**--------------------------------------------------------------------------**/
265 /**
266  * @brief ETH Frames defines
267  */
268 /**--------------------------------------------------------------------------**/
269 
270 /** @defgroup ENET_Buffers_setting
271  * @{
272  */
273 #define ETH_MAX_PACKET_SIZE 1524 /*!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
274 #define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
275 #define ETH_CRC 4 /*!< Ethernet CRC */
276 #define ETH_EXTRA 2 /*!< Extra bytes in some cases */
277 #define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */
278 #define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */
279 #define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */
280 #define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */
281 
282  /* Ethernet driver receive buffers are organized in a chained linked-list, when
283  an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
284  to the driver receive buffers memory.
285 
286  Depending on the size of the received ethernet packet and the size of
287  each ethernet driver receive buffer, the received packet can take one or more
288  ethernet driver receive buffer.
289 
290  In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
291  and the total count of the driver receive buffers ETH_RXBUFNB.
292 
293  The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
294  example, they can be reconfigured in the application layer to fit the application
295  needs */
296 
297 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
298  packet */
299 #ifndef ETH_RX_BUF_SIZE
300  #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
301 #endif
302 
303 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
304 #ifndef ETH_RXBUFNB
305  #define ETH_RXBUFNB 5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
306 #endif
307 
308 
309  /* Ethernet driver transmit buffers are organized in a chained linked-list, when
310  an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
311  driver transmit buffers memory to the TxFIFO.
312 
313  Depending on the size of the Ethernet packet to be transmitted and the size of
314  each ethernet driver transmit buffer, the packet to be transmitted can take
315  one or more ethernet driver transmit buffer.
316 
317  In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
318  and the total count of the driver transmit buffers ETH_TXBUFNB.
319 
320  The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
321  example, they can be reconfigured in the application layer to fit the application
322  needs */
323 
324 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
325  packet */
326 #ifndef ETH_TX_BUF_SIZE
327  #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
328 #endif
329 
330 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
331 #ifndef ETH_TXBUFNB
332  #define ETH_TXBUFNB 5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
333 #endif
334 
335 #define ETH_DMARxDesc_FrameLengthShift 16
336 
337 /**--------------------------------------------------------------------------**/
338 /**
339  * @brief Ethernet DMA descriptors registers bits definition
340  */
341 /**--------------------------------------------------------------------------**/
342 
343 /**
344 @code
345  DMA Tx Desciptor
346  -----------------------------------------------------------------------------------------------
347  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
348  -----------------------------------------------------------------------------------------------
349  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
350  -----------------------------------------------------------------------------------------------
351  TDES2 | Buffer1 Address [31:0] |
352  -----------------------------------------------------------------------------------------------
353  TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
354  -----------------------------------------------------------------------------------------------
355 @endcode
356 */
357 
358 /**
359  * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
360  */
361 #define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
362 #define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
363 #define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */
364 #define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */
365 #define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */
366 #define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */
367 #define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
368 #define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
369 #define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
370 #define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
371 #define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
372 #define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
373 #define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
374 #define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
375 #define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
376 #define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
377 #define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
378 #define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
379 #define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
380 #define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
381 #define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
382 #define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
383 #define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
384 #define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
385 #define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
386 #define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */
387 #define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
388 #define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
389 #define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
390 
391 /**
392  * @brief Bit definition of TDES1 register
393  */
394 #define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
395 #define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
396 
397 /**
398  * @brief Bit definition of TDES2 register
399  */
400 #define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
401 
402 /**
403  * @brief Bit definition of TDES3 register
404  */
405 #define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
406 
407  /*---------------------------------------------------------------------------------------------
408  TDES6 | Transmit Time Stamp Low [31:0] |
409  -----------------------------------------------------------------------------------------------
410  TDES7 | Transmit Time Stamp High [31:0] |
411  ----------------------------------------------------------------------------------------------*/
412 
413 /* Bit definition of TDES6 register */
414  #define ETH_DMAPTPTxDesc_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
415 
416 /* Bit definition of TDES7 register */
417  #define ETH_DMAPTPTxDesc_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
418 
419 /**
420  * @}
421  */
422 
423 
424 /** @defgroup DMA_Rx_descriptor
425  * @{
426  */
427 
428 /**
429 @code
430  DMA Rx Descriptor
431  --------------------------------------------------------------------------------------------------------------------
432  RDES0 | OWN(31) | Status [30:0] |
433  ---------------------------------------------------------------------------------------------------------------------
434  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
435  ---------------------------------------------------------------------------------------------------------------------
436  RDES2 | Buffer1 Address [31:0] |
437  ---------------------------------------------------------------------------------------------------------------------
438  RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
439  ---------------------------------------------------------------------------------------------------------------------
440 @endcode
441 */
442 
443 /**
444  * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
445  */
446 #define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
447 #define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
448 #define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
449 #define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
450 #define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
451 #define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
452 #define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
453 #define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
454 #define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
455 #define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
456 #define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
457 #define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
458 #define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
459 #define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
460 #define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
461 #define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
462 #define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
463 #define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */
464 #define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
465 
466 /**
467  * @brief Bit definition of RDES1 register
468  */
469 #define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
470 #define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
471 #define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
472 #define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
473 #define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
474 
475 /**
476  * @brief Bit definition of RDES2 register
477  */
478 #define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
479 
480 /**
481  * @brief Bit definition of RDES3 register
482  */
483 #define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
484 
485 /*---------------------------------------------------------------------------------------------------------------------
486  RDES4 | Reserved[31:15] | Extended Status [14:0] |
487  ---------------------------------------------------------------------------------------------------------------------
488  RDES5 | Reserved[31:0] |
489  ---------------------------------------------------------------------------------------------------------------------
490  RDES6 | Receive Time Stamp Low [31:0] |
491  ---------------------------------------------------------------------------------------------------------------------
492  RDES7 | Receive Time Stamp High [31:0] |
493  --------------------------------------------------------------------------------------------------------------------*/
494 
495 /* Bit definition of RDES4 register */
496 #define ETH_DMAPTPRxDesc_PTPV ((uint32_t)0x00002000) /* PTP Version */
497 #define ETH_DMAPTPRxDesc_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
498 #define ETH_DMAPTPRxDesc_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
499  #define ETH_DMAPTPRxDesc_PTPMT_Sync ((uint32_t)0x00000100) /* SYNC message (all clock types) */
500  #define ETH_DMAPTPRxDesc_PTPMT_FollowUp ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
501  #define ETH_DMAPTPRxDesc_PTPMT_DelayReq ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
502  #define ETH_DMAPTPRxDesc_PTPMT_DelayResp ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
503  #define ETH_DMAPTPRxDesc_PTPMT_PdelayReq_Announce ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
504  #define ETH_DMAPTPRxDesc_PTPMT_PdelayResp_Manag ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
505  #define ETH_DMAPTPRxDesc_PTPMT_PdelayRespFollowUp_Signal ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
506 #define ETH_DMAPTPRxDesc_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
507 #define ETH_DMAPTPRxDesc_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
508 #define ETH_DMAPTPRxDesc_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
509 #define ETH_DMAPTPRxDesc_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
510 #define ETH_DMAPTPRxDesc_IPHE ((uint32_t)0x00000008) /* IP Header Error */
511 #define ETH_DMAPTPRxDesc_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
512  #define ETH_DMAPTPRxDesc_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
513  #define ETH_DMAPTPRxDesc_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
514  #define ETH_DMAPTPRxDesc_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
515 
516 /* Bit definition of RDES6 register */
517 #define ETH_DMAPTPRxDesc_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
518 
519 /* Bit definition of RDES7 register */
520 #define ETH_DMAPTPRxDesc_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
521 
522 
523 /**--------------------------------------------------------------------------**/
524 /**
525  * @brief Description of common PHY registers
526  */
527 /**--------------------------------------------------------------------------**/
528 
529 /**
530  * @}
531  */
532 
533 /** @defgroup PHY_Read_write_Timeouts
534  * @{
535  */
536 #define PHY_READ_TO ((uint32_t)0x0004FFFF)
537 #define PHY_WRITE_TO ((uint32_t)0x0004FFFF)
538 
539 /**
540  * @}
541  */
542 
543 /** @defgroup PHY_Register_address
544  * @{
545  */
546 #define PHY_BCR 0 /*!< Transceiver Basic Control Register */
547 #define PHY_BSR 1 /*!< Transceiver Basic Status Register */
548 
549 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
550 #define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
551  ((REG) == PHY_BSR) || \
552  ((REG) == PHY_SR))
553 /**
554  * @}
555  */
556 
557 /** @defgroup PHY_basic_Control_register
558  * @{
559  */
560 #define PHY_Reset ((uint16_t)0x8000) /*!< PHY Reset */
561 #define PHY_Loopback ((uint16_t)0x4000) /*!< Select loop-back mode */
562 #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
563 #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
564 #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
565 #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
566 #define PHY_AutoNegotiation ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
567 #define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
568 #define PHY_Powerdown ((uint16_t)0x0800) /*!< Select the power down mode */
569 #define PHY_Isolate ((uint16_t)0x0400) /*!< Isolate PHY from MII */
570 
571 /**
572  * @}
573  */
574 
575 /** @defgroup PHY_basic_status_register
576  * @{
577  */
578 #define PHY_AutoNego_Complete ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
579 #define PHY_Linked_Status ((uint16_t)0x0004) /*!< Valid link established */
580 #define PHY_Jabber_detection ((uint16_t)0x0002) /*!< Jabber condition detected */
581 
582 /**
583  * @}
584  */
585 
586 /**--------------------------------------------------------------------------**/
587 /**
588  * @brief MAC defines
589  */
590 /**--------------------------------------------------------------------------**/
591 
592 /** @defgroup ETH_AutoNegotiation
593  * @{
594  */
595 #define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001)
596 #define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000)
597 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
598  ((CMD) == ETH_AutoNegotiation_Disable))
599 
600 /**
601  * @}
602  */
603 
604 /** @defgroup ETH_watchdog
605  * @{
606  */
607 #define ETH_Watchdog_Enable ((uint32_t)0x00000000)
608 #define ETH_Watchdog_Disable ((uint32_t)0x00800000)
609 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
610  ((CMD) == ETH_Watchdog_Disable))
611 
612 /**
613  * @}
614  */
615 
616 /** @defgroup ETH_Jabber
617  * @{
618  */
619 #define ETH_Jabber_Enable ((uint32_t)0x00000000)
620 #define ETH_Jabber_Disable ((uint32_t)0x00400000)
621 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
622  ((CMD) == ETH_Jabber_Disable))
623 
624 /**
625  * @}
626  */
627 
628 /** @defgroup ETH_Inter_Frame_Gap
629  * @{
630  */
631 #define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
632 #define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
633 #define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
634 #define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
635 #define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
636 #define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
637 #define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
638 #define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
639 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
640  ((GAP) == ETH_InterFrameGap_88Bit) || \
641  ((GAP) == ETH_InterFrameGap_80Bit) || \
642  ((GAP) == ETH_InterFrameGap_72Bit) || \
643  ((GAP) == ETH_InterFrameGap_64Bit) || \
644  ((GAP) == ETH_InterFrameGap_56Bit) || \
645  ((GAP) == ETH_InterFrameGap_48Bit) || \
646  ((GAP) == ETH_InterFrameGap_40Bit))
647 
648 /**
649  * @}
650  */
651 
652 /** @defgroup ETH_Carrier_Sense
653  * @{
654  */
655 #define ETH_CarrierSense_Enable ((uint32_t)0x00000000)
656 #define ETH_CarrierSense_Disable ((uint32_t)0x00010000)
657 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
658  ((CMD) == ETH_CarrierSense_Disable))
659 
660 /**
661  * @}
662  */
663 
664 /** @defgroup ETH_Speed
665  * @{
666  */
667 #define ETH_Speed_10M ((uint32_t)0x00000000)
668 #define ETH_Speed_100M ((uint32_t)0x00004000)
669 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
670  ((SPEED) == ETH_Speed_100M))
671 
672 /**
673  * @}
674  */
675 
676 /** @defgroup ETH_Receive_Own
677  * @{
678  */
679 #define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000)
680 #define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000)
681 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
682  ((CMD) == ETH_ReceiveOwn_Disable))
683 
684 /**
685  * @}
686  */
687 
688 /** @defgroup ETH_Loop_Back_Mode
689  * @{
690  */
691 #define ETH_LoopbackMode_Enable ((uint32_t)0x00001000)
692 #define ETH_LoopbackMode_Disable ((uint32_t)0x00000000)
693 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
694  ((CMD) == ETH_LoopbackMode_Disable))
695 
696 /**
697  * @}
698  */
699 
700 /** @defgroup ETH_Duplex_Mode
701  * @{
702  */
703 #define ETH_Mode_FullDuplex ((uint32_t)0x00000800)
704 #define ETH_Mode_HalfDuplex ((uint32_t)0x00000000)
705 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
706  ((MODE) == ETH_Mode_HalfDuplex))
707 
708 /**
709  * @}
710  */
711 
712 /** @defgroup ETH_Checksum_Offload
713  * @{
714  */
715 #define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400)
716 #define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000)
717 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
718  ((CMD) == ETH_ChecksumOffload_Disable))
719 
720 /**
721  * @}
722  */
723 
724 /** @defgroup ETH_Retry_Transmission
725  * @{
726  */
727 #define ETH_RetryTransmission_Enable ((uint32_t)0x00000000)
728 #define ETH_RetryTransmission_Disable ((uint32_t)0x00000200)
729 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
730  ((CMD) == ETH_RetryTransmission_Disable))
731 
732 /**
733  * @}
734  */
735 
736 /** @defgroup ETH_Automatic_Pad_CRC_Strip
737  * @{
738  */
739 #define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080)
740 #define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000)
741 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
742  ((CMD) == ETH_AutomaticPadCRCStrip_Disable))
743 
744 /**
745  * @}
746  */
747 
748 /** @defgroup ETH_Back_Off_Limit
749  * @{
750  */
751 #define ETH_BackOffLimit_10 ((uint32_t)0x00000000)
752 #define ETH_BackOffLimit_8 ((uint32_t)0x00000020)
753 #define ETH_BackOffLimit_4 ((uint32_t)0x00000040)
754 #define ETH_BackOffLimit_1 ((uint32_t)0x00000060)
755 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
756  ((LIMIT) == ETH_BackOffLimit_8) || \
757  ((LIMIT) == ETH_BackOffLimit_4) || \
758  ((LIMIT) == ETH_BackOffLimit_1))
759 
760 /**
761  * @}
762  */
763 
764 /** @defgroup ETH_Deferral_Check
765  * @{
766  */
767 #define ETH_DeferralCheck_Enable ((uint32_t)0x00000010)
768 #define ETH_DeferralCheck_Disable ((uint32_t)0x00000000)
769 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
770  ((CMD) == ETH_DeferralCheck_Disable))
771 
772 /**
773  * @}
774  */
775 
776 /** @defgroup ETH_Receive_All
777  * @{
778  */
779 #define ETH_ReceiveAll_Enable ((uint32_t)0x80000000)
780 #define ETH_ReceiveAll_Disable ((uint32_t)0x00000000)
781 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
782  ((CMD) == ETH_ReceiveAll_Disable))
783 
784 /**
785  * @}
786  */
787 
788 /** @defgroup ETH_Source_Addr_Filter
789  * @{
790  */
791 #define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200)
792 #define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300)
793 #define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000)
794 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
795  ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \
796  ((CMD) == ETH_SourceAddrFilter_Disable))
797 
798 /**
799  * @}
800  */
801 
802 /** @defgroup ETH_Pass_Control_Frames
803  * @{
804  */
805 #define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
806 #define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
807 #define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
808 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
809  ((PASS) == ETH_PassControlFrames_ForwardAll) || \
810  ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))
811 
812 /**
813  * @}
814  */
815 
816 /** @defgroup ETH_Broadcast_Frames_Reception
817  * @{
818  */
819 #define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000)
820 #define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020)
821 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
822  ((CMD) == ETH_BroadcastFramesReception_Disable))
823 
824 /**
825  * @}
826  */
827 
828 /** @defgroup ETH_Destination_Addr_Filter
829  * @{
830  */
831 #define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000)
832 #define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008)
833 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
834  ((FILTER) == ETH_DestinationAddrFilter_Inverse))
835 
836 /**
837  * @}
838  */
839 
840 /** @defgroup ETH_Promiscuous_Mode
841  * @{
842  */
843 #define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001)
844 #define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000)
845 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
846  ((CMD) == ETH_PromiscuousMode_Disable))
847 
848 /**
849  * @}
850  */
851 
852 /** @defgroup ETH_Multicast_Frames_Filter
853  * @{
854  */
855 #define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404)
856 #define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004)
857 #define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000)
858 #define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010)
859 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
860  ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \
861  ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \
862  ((FILTER) == ETH_MulticastFramesFilter_None))
863 
864 
865 /**
866  * @}
867  */
868 
869 /** @defgroup ETH_Unicast_Frames_Filter
870  * @{
871  */
872 #define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402)
873 #define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002)
874 #define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000)
875 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
876  ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \
877  ((FILTER) == ETH_UnicastFramesFilter_Perfect))
878 
879 /**
880  * @}
881  */
882 
883 /** @defgroup ETH_Pause_Time
884  * @{
885  */
886 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
887 
888 /**
889  * @}
890  */
891 
892 /** @defgroup ETH_Zero_Quanta_Pause
893  * @{
894  */
895 #define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000)
896 #define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080)
897 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \
898  ((CMD) == ETH_ZeroQuantaPause_Disable))
899 /**
900  * @}
901  */
902 
903 /** @defgroup ETH_Pause_Low_Threshold
904  * @{
905  */
906 #define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
907 #define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
908 #define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
909 #define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
910 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
911  ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \
912  ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \
913  ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))
914 
915 /**
916  * @}
917  */
918 
919 /** @defgroup ETH_Unicast_Pause_Frame_Detect
920  * @{
921  */
922 #define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008)
923 #define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000)
924 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
925  ((CMD) == ETH_UnicastPauseFrameDetect_Disable))
926 
927 /**
928  * @}
929  */
930 
931 /** @defgroup ETH_Receive_Flow_Control
932  * @{
933  */
934 #define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004)
935 #define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000)
936 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
937  ((CMD) == ETH_ReceiveFlowControl_Disable))
938 
939 /**
940  * @}
941  */
942 
943 /** @defgroup ETH_Transmit_Flow_Control
944  * @{
945  */
946 #define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002)
947 #define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000)
948 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
949  ((CMD) == ETH_TransmitFlowControl_Disable))
950 
951 /**
952  * @}
953  */
954 
955 /** @defgroup ETH_VLAN_Tag_Comparison
956  * @{
957  */
958 #define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000)
959 #define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000)
960 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
961  ((COMPARISON) == ETH_VLANTagComparison_16Bit))
962 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
963 
964 /**
965  * @}
966  */
967 
968 /** @defgroup ETH_MAC_Flags
969  * @{
970  */
971 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
972 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
973 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
974 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
975 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
976 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
977  ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
978  ((FLAG) == ETH_MAC_FLAG_PMT))
979 /**
980  * @}
981  */
982 
983 /** @defgroup ETH_MAC_Interrupts
984  * @{
985  */
986 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
987 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
988 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
989 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
990 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
991 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
992 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
993  ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
994  ((IT) == ETH_MAC_IT_PMT))
995 /**
996  * @}
997  */
998 
999 /** @defgroup ETH_MAC_addresses
1000  * @{
1001  */
1002 #define ETH_MAC_Address0 ((uint32_t)0x00000000)
1003 #define ETH_MAC_Address1 ((uint32_t)0x00000008)
1004 #define ETH_MAC_Address2 ((uint32_t)0x00000010)
1005 #define ETH_MAC_Address3 ((uint32_t)0x00000018)
1006 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
1007  ((ADDRESS) == ETH_MAC_Address1) || \
1008  ((ADDRESS) == ETH_MAC_Address2) || \
1009  ((ADDRESS) == ETH_MAC_Address3))
1010 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
1011  ((ADDRESS) == ETH_MAC_Address2) || \
1012  ((ADDRESS) == ETH_MAC_Address3))
1013 /**
1014  * @}
1015  */
1016 
1017 /** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
1018  * @{
1019  */
1020 #define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000)
1021 #define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008)
1022 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
1023  ((FILTER) == ETH_MAC_AddressFilter_DA))
1024 /**
1025  * @}
1026  */
1027 
1028 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes
1029  * @{
1030  */
1031 #define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
1032 #define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
1033 #define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
1034 #define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
1035 #define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
1036 #define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
1037 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
1038  ((MASK) == ETH_MAC_AddressMask_Byte5) || \
1039  ((MASK) == ETH_MAC_AddressMask_Byte4) || \
1040  ((MASK) == ETH_MAC_AddressMask_Byte3) || \
1041  ((MASK) == ETH_MAC_AddressMask_Byte2) || \
1042  ((MASK) == ETH_MAC_AddressMask_Byte1))
1043 
1044 /**--------------------------------------------------------------------------**/
1045 /**
1046  * @brief Ethernet DMA Descriptors defines
1047  */
1048 /**--------------------------------------------------------------------------**/
1049 /**
1050  * @}
1051  */
1052 
1053 /** @defgroup ETH_DMA_Tx_descriptor_flags
1054  * @{
1055  */
1056 #define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
1057  ((FLAG) == ETH_DMATxDesc_IC) || \
1058  ((FLAG) == ETH_DMATxDesc_LS) || \
1059  ((FLAG) == ETH_DMATxDesc_FS) || \
1060  ((FLAG) == ETH_DMATxDesc_DC) || \
1061  ((FLAG) == ETH_DMATxDesc_DP) || \
1062  ((FLAG) == ETH_DMATxDesc_TTSE) || \
1063  ((FLAG) == ETH_DMATxDesc_TER) || \
1064  ((FLAG) == ETH_DMATxDesc_TCH) || \
1065  ((FLAG) == ETH_DMATxDesc_TTSS) || \
1066  ((FLAG) == ETH_DMATxDesc_IHE) || \
1067  ((FLAG) == ETH_DMATxDesc_ES) || \
1068  ((FLAG) == ETH_DMATxDesc_JT) || \
1069  ((FLAG) == ETH_DMATxDesc_FF) || \
1070  ((FLAG) == ETH_DMATxDesc_PCE) || \
1071  ((FLAG) == ETH_DMATxDesc_LCA) || \
1072  ((FLAG) == ETH_DMATxDesc_NC) || \
1073  ((FLAG) == ETH_DMATxDesc_LCO) || \
1074  ((FLAG) == ETH_DMATxDesc_EC) || \
1075  ((FLAG) == ETH_DMATxDesc_VF) || \
1076  ((FLAG) == ETH_DMATxDesc_CC) || \
1077  ((FLAG) == ETH_DMATxDesc_ED) || \
1078  ((FLAG) == ETH_DMATxDesc_UF) || \
1079  ((FLAG) == ETH_DMATxDesc_DB))
1080 
1081 /**
1082  * @}
1083  */
1084 
1085 /** @defgroup ETH_DMA_Tx_descriptor_segment
1086  * @{
1087  */
1088 #define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */
1089 #define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */
1090 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
1091  ((SEGMENT) == ETH_DMATxDesc_FirstSegment))
1092 
1093 /**
1094  * @}
1095  */
1096 
1097 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
1098  * @{
1099  */
1100 #define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */
1101 #define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
1102 #define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
1103 #define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
1104 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
1105  ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \
1106  ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \
1107  ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))
1108 /**
1109  * @brief ETH DMA Tx Desciptor buffer size
1110  */
1111 #define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
1112 
1113 /**
1114  * @}
1115  */
1116 
1117 /** @defgroup ETH_DMA_Rx_descriptor_flags
1118  * @{
1119  */
1120 #define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
1121  ((FLAG) == ETH_DMARxDesc_AFM) || \
1122  ((FLAG) == ETH_DMARxDesc_ES) || \
1123  ((FLAG) == ETH_DMARxDesc_DE) || \
1124  ((FLAG) == ETH_DMARxDesc_SAF) || \
1125  ((FLAG) == ETH_DMARxDesc_LE) || \
1126  ((FLAG) == ETH_DMARxDesc_OE) || \
1127  ((FLAG) == ETH_DMARxDesc_VLAN) || \
1128  ((FLAG) == ETH_DMARxDesc_FS) || \
1129  ((FLAG) == ETH_DMARxDesc_LS) || \
1130  ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \
1131  ((FLAG) == ETH_DMARxDesc_LC) || \
1132  ((FLAG) == ETH_DMARxDesc_FT) || \
1133  ((FLAG) == ETH_DMARxDesc_RWT) || \
1134  ((FLAG) == ETH_DMARxDesc_RE) || \
1135  ((FLAG) == ETH_DMARxDesc_DBE) || \
1136  ((FLAG) == ETH_DMARxDesc_CE) || \
1137  ((FLAG) == ETH_DMARxDesc_MAMPCE))
1138 
1139 /* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
1140 #define IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRxDesc_PTPV) || \
1141  ((FLAG) == ETH_DMAPTPRxDesc_PTPFT) || \
1142  ((FLAG) == ETH_DMAPTPRxDesc_PTPMT) || \
1143  ((FLAG) == ETH_DMAPTPRxDesc_IPV6PR) || \
1144  ((FLAG) == ETH_DMAPTPRxDesc_IPV4PR) || \
1145  ((FLAG) == ETH_DMAPTPRxDesc_IPCB) || \
1146  ((FLAG) == ETH_DMAPTPRxDesc_IPPE) || \
1147  ((FLAG) == ETH_DMAPTPRxDesc_IPHE) || \
1148  ((FLAG) == ETH_DMAPTPRxDesc_IPPT))
1149 
1150 /**
1151  * @}
1152  */
1153 
1154 /** @defgroup ETH_DMA_Rx_descriptor_buffers_
1155  * @{
1156  */
1157 #define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
1158 #define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
1159 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
1160  ((BUFFER) == ETH_DMARxDesc_Buffer2))
1161 
1162 /**--------------------------------------------------------------------------**/
1163 /**
1164  * @brief Ethernet DMA defines
1165  */
1166 /**--------------------------------------------------------------------------**/
1167 /**
1168  * @}
1169  */
1170 
1171 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
1172  * @{
1173  */
1174 #define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000)
1175 #define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000)
1176 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
1177  ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))
1178 /**
1179  * @}
1180  */
1181 
1182 /** @defgroup ETH_Receive_Store_Forward
1183  * @{
1184  */
1185 #define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000)
1186 #define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000)
1187 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
1188  ((CMD) == ETH_ReceiveStoreForward_Disable))
1189 /**
1190  * @}
1191  */
1192 
1193 /** @defgroup ETH_Flush_Received_Frame
1194  * @{
1195  */
1196 #define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000)
1197 #define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000)
1198 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
1199  ((CMD) == ETH_FlushReceivedFrame_Disable))
1200 /**
1201  * @}
1202  */
1203 
1204 /** @defgroup ETH_Transmit_Store_Forward
1205  * @{
1206  */
1207 #define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000)
1208 #define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000)
1209 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
1210  ((CMD) == ETH_TransmitStoreForward_Disable))
1211 /**
1212  * @}
1213  */
1214 
1215 /** @defgroup ETH_Transmit_Threshold_Control
1216  * @{
1217  */
1218 #define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
1219 #define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
1220 #define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
1221 #define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
1222 #define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
1223 #define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
1224 #define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
1225 #define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
1226 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
1227  ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \
1228  ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \
1229  ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \
1230  ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \
1231  ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \
1232  ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \
1233  ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))
1234 /**
1235  * @}
1236  */
1237 
1238 /** @defgroup ETH_Forward_Error_Frames
1239  * @{
1240  */
1241 #define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080)
1242 #define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000)
1243 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
1244  ((CMD) == ETH_ForwardErrorFrames_Disable))
1245 /**
1246  * @}
1247  */
1248 
1249 /** @defgroup ETH_Forward_Undersized_Good_Frames
1250  * @{
1251  */
1252 #define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040)
1253 #define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000)
1254 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
1255  ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))
1256 
1257 /**
1258  * @}
1259  */
1260 
1261 /** @defgroup ETH_Receive_Threshold_Control
1262  * @{
1263  */
1264 #define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
1265 #define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
1266 #define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
1267 #define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
1268 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
1269  ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \
1270  ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \
1271  ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))
1272 /**
1273  * @}
1274  */
1275 
1276 /** @defgroup ETH_Second_Frame_Operate
1277  * @{
1278  */
1279 #define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004)
1280 #define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000)
1281 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
1282  ((CMD) == ETH_SecondFrameOperate_Disable))
1283 
1284 /**
1285  * @}
1286  */
1287 
1288 /** @defgroup ETH_Address_Aligned_Beats
1289  * @{
1290  */
1291 #define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000)
1292 #define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000)
1293 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
1294  ((CMD) == ETH_AddressAlignedBeats_Disable))
1295 
1296 /**
1297  * @}
1298  */
1299 
1300 /** @defgroup ETH_Fixed_Burst
1301  * @{
1302  */
1303 #define ETH_FixedBurst_Enable ((uint32_t)0x00010000)
1304 #define ETH_FixedBurst_Disable ((uint32_t)0x00000000)
1305 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
1306  ((CMD) == ETH_FixedBurst_Disable))
1307 
1308 /**
1309  * @}
1310  */
1311 
1312 /** @defgroup ETH_Rx_DMA_Burst_Length
1313  * @{
1314  */
1315 #define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
1316 #define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
1317 #define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1318 #define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1319 #define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1320 #define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1321 #define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1322 #define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1323 #define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1324 #define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1325 #define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
1326 #define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
1327 
1328 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
1329  ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \
1330  ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \
1331  ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \
1332  ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \
1333  ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \
1334  ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \
1335  ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \
1336  ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \
1337  ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \
1338  ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \
1339  ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))
1340 
1341 /**
1342  * @}
1343  */
1344 
1345 /** @defgroup ETH_Tx_DMA_Burst_Length
1346  * @{
1347  */
1348 #define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
1349 #define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
1350 #define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1351 #define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1352 #define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1353 #define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1354 #define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1355 #define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1356 #define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1357 #define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1358 #define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
1359 #define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
1360 
1361 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
1362  ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \
1363  ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \
1364  ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \
1365  ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \
1366  ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \
1367  ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \
1368  ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \
1369  ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \
1370  ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \
1371  ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \
1372  ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))
1373 /**
1374  * @brief ETH DMA Descriptor SkipLength
1375  */
1376 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
1377 
1378 /**
1379  * @}
1380  */
1381 
1382 /** @defgroup ETH_DMA_Arbitration
1383  * @{
1384  */
1385 #define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000)
1386 #define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000)
1387 #define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000)
1388 #define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000)
1389 #define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002)
1390 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
1391  ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \
1392  ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \
1393  ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \
1394  ((RATIO) == ETH_DMAArbitration_RxPriorTx))
1395 /**
1396  * @}
1397  */
1398 
1399 /** @defgroup ETH_DMA_Flags
1400  * @{
1401  */
1402 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
1403 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
1404 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
1405 #define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
1406 #define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
1407 #define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
1408 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
1409 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
1410 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
1411 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
1412 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
1413 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
1414 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
1415 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
1416 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
1417 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
1418 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
1419 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
1420 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
1421 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
1422 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
1423 
1424 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00))
1425 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
1426  ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \
1427  ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \
1428  ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
1429  ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
1430  ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
1431  ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
1432  ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
1433  ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
1434  ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
1435  ((FLAG) == ETH_DMA_FLAG_T))
1436 /**
1437  * @}
1438  */
1439 
1440 /** @defgroup ETH_DMA_Interrupts
1441  * @{
1442  */
1443 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
1444 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
1445 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
1446 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
1447 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
1448 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
1449 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
1450 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
1451 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
1452 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
1453 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
1454 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
1455 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
1456 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
1457 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
1458 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
1459 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
1460 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
1461 
1462 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00))
1463 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
1464  ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
1465  ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
1466  ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
1467  ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
1468  ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
1469  ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
1470  ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
1471  ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
1472 
1473 /**
1474  * @}
1475  */
1476 
1477 /** @defgroup ETH_DMA_transmit_process_state_
1478  * @{
1479  */
1480 #define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
1481 #define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
1482 #define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */
1483 #define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
1484 #define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
1485 #define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
1486 
1487 /**
1488  * @}
1489  */
1490 
1491 
1492 /** @defgroup ETH_DMA_receive_process_state_
1493  * @{
1494  */
1495 #define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
1496 #define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
1497 #define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */
1498 #define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
1499 #define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
1500 #define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
1501 
1502 /**
1503  * @}
1504  */
1505 
1506 /** @defgroup ETH_DMA_overflow_
1507  * @{
1508  */
1509 #define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
1510 #define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
1511 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
1512  ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))
1513 
1514 /**--------------------------------------------------------------------------**/
1515 /**
1516  * @brief Ethernet PMT defines
1517  */
1518 /**--------------------------------------------------------------------------**/
1519 /**
1520  * @}
1521  */
1522 
1523 /** @defgroup ETH_PMT_Flags
1524  * @{
1525  */
1526 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
1527 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
1528 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
1529 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
1530  ((FLAG) == ETH_PMT_FLAG_MPR))
1531 
1532 /**--------------------------------------------------------------------------**/
1533 /**
1534  * @brief Ethernet MMC defines
1535  */
1536 /**--------------------------------------------------------------------------**/
1537 /**
1538  * @}
1539  */
1540 
1541 /** @defgroup ETH_MMC_Tx_Interrupts
1542  * @{
1543  */
1544 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
1545 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
1546 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
1547 
1548 /**
1549  * @}
1550  */
1551 
1552 /** @defgroup ETH_MMC_Rx_Interrupts
1553  * @{
1554  */
1555 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
1556 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
1557 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
1558 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
1559  ((IT) != 0x00))
1560 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
1561  ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
1562  ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
1563 /**
1564  * @}
1565  */
1566 
1567 /** @defgroup ETH_MMC_Registers
1568  * @{
1569  */
1570 #define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */
1571 #define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */
1572 #define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */
1573 #define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */
1574 #define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */
1575 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */
1576 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */
1577 #define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */
1578 #define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */
1579 #define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */
1580 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */
1581 
1582 /**
1583  * @brief ETH MMC registers
1584  */
1585 #define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
1586  ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
1587  ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
1588  ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
1589  ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
1590  ((REG) == ETH_MMCRGUFCR))
1591 
1592 /**--------------------------------------------------------------------------**/
1593 /**
1594  * @brief Ethernet PTP defines
1595  */
1596 /**--------------------------------------------------------------------------**/
1597 /**
1598  * @}
1599  */
1600 
1601 /** @defgroup ETH_PTP_time_update_method
1602  * @{
1603  */
1604 #define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */
1605 #define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */
1606 #define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
1607  ((UPDATE) == ETH_PTP_CoarseUpdate))
1608 
1609 /**
1610  * @}
1611  */
1612 
1613 
1614 /** @defgroup ETH_PTP_Flags
1615  * @{
1616  */
1617 #define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */
1618 #define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */
1619 #define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */
1620 #define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */
1621 
1622 #define ETH_PTP_FLAG_TSTTR ((uint32_t)0x10000002) /* Time stamp target time reached */
1623 #define ETH_PTP_FLAG_TSSO ((uint32_t)0x10000001) /* Time stamp seconds overflow */
1624 
1625 #define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
1626  ((FLAG) == ETH_PTP_FLAG_TSITE) || \
1627  ((FLAG) == ETH_PTP_FLAG_TSSTU) || \
1628  ((FLAG) == ETH_PTP_FLAG_TSSTI) || \
1629  ((FLAG) == ETH_PTP_FLAG_TSTTR) || \
1630  ((FLAG) == ETH_PTP_FLAG_TSSO))
1631 
1632 /**
1633  * @brief ETH PTP subsecond increment
1634  */
1635 #define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)
1636 
1637 /**
1638  * @}
1639  */
1640 
1641 
1642 /** @defgroup ETH_PTP_time_sign
1643  * @{
1644  */
1645 #define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */
1646 #define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */
1647 #define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
1648  ((SIGN) == ETH_PTP_NegativeTime))
1649 
1650 /**
1651  * @brief ETH PTP time stamp low update
1652  */
1653 #define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)
1654 
1655 /**
1656  * @brief ETH PTP registers
1657  */
1658 #define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */
1659 #define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */
1660 #define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */
1661 #define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */
1662 #define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */
1663 #define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */
1664 #define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */
1665 #define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */
1666 #define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */
1667 
1668 #define ETH_PTPTSSR ((uint32_t)0x00000728) /* PTP TSSR register */
1669 
1670 #define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
1671  ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \
1672  ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \
1673  ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \
1674  ((REG) == ETH_PTPTTLR) || ((REG) == ETH_PTPTSSR))
1675 
1676 /**
1677  * @brief ETHERNET PTP clock
1678  */
1679 #define ETH_PTP_OrdinaryClock ((uint32_t)0x00000000) /* Ordinary Clock */
1680 #define ETH_PTP_BoundaryClock ((uint32_t)0x00010000) /* Boundary Clock */
1681 #define ETH_PTP_EndToEndTransparentClock ((uint32_t)0x00020000) /* End To End Transparent Clock */
1682 #define ETH_PTP_PeerToPeerTransparentClock ((uint32_t)0x00030000) /* Peer To Peer Transparent Clock */
1683 
1684 #define IS_ETH_PTP_TYPE_CLOCK(CLOCK) (((CLOCK) == ETH_PTP_OrdinaryClock) || \
1685  ((CLOCK) == ETH_PTP_BoundaryClock) || \
1686  ((CLOCK) == ETH_PTP_EndToEndTransparentClock) || \
1687  ((CLOCK) == ETH_PTP_PeerToPeerTransparentClock))
1688 /**
1689  * @brief ETHERNET snapshot
1690  */
1691 #define ETH_PTP_SnapshotMasterMessage ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
1692 #define ETH_PTP_SnapshotEventMessage ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
1693 #define ETH_PTP_SnapshotIPV4Frames ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
1694 #define ETH_PTP_SnapshotIPV6Frames ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
1695 #define ETH_PTP_SnapshotPTPOverEthernetFrames ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
1696 #define ETH_PTP_SnapshotAllReceivedFrames ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
1697 
1698 #define IS_ETH_PTP_SNAPSHOT(SNAPSHOT) (((SNAPSHOT) == ETH_PTP_SnapshotMasterMessage) || \
1699  ((SNAPSHOT) == ETH_PTP_SnapshotEventMessage) || \
1700  ((SNAPSHOT) == ETH_PTP_SnapshotIPV4Frames) || \
1701  ((SNAPSHOT) == ETH_PTP_SnapshotIPV6Frames) || \
1702  ((SNAPSHOT) == ETH_PTP_SnapshotPTPOverEthernetFrames) || \
1703  ((SNAPSHOT) == ETH_PTP_SnapshotAllReceivedFrames))
1704 
1705 /**
1706  * @}
1707  */
1708 /* ETHERNET MAC address offsets */
1709 #define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */
1710 #define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */
1711 
1712 /* ETHERNET MACMIIAR register Mask */
1713 #define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
1714 
1715 /* ETHERNET MACCR register Mask */
1716 #define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
1717 
1718 /* ETHERNET MACFCR register Mask */
1719 #define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
1720 
1721 
1722 /* ETHERNET DMAOMR register Mask */
1723 #define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
1724 
1725 
1726 /* ETHERNET Remote Wake-up frame register length */
1727 #define ETH_WAKEUP_REGISTER_LENGTH 8
1728 
1729 /* ETHERNET Missed frames counter Shift */
1730 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
1731 
1732 /* ETHERNET DMA Tx descriptors Collision Count Shift */
1733 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3
1734 
1735 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
1736 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16
1737 
1738 /* ETHERNET DMA Rx descriptors Frame Length Shift */
1739 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16
1740 
1741 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
1742 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16
1743 
1744 /* ETHERNET errors */
1745 #define ETH_ERROR ((uint32_t)0)
1746 #define ETH_SUCCESS ((uint32_t)1)
1747 
1748 /**
1749  * @}
1750  */
1751 
1752 /** @defgroup ETH_Exported_Macros
1753  * @{
1754  */
1755 /**
1756  * @}
1757  */
1758 
1759 /** @defgroup ETH_Exported_Functions
1760  * @{
1761  */
1762 void ETH_Init_MII_Only(void);
1763 void ETH_DeInit(void);
1764 uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress);
1765 void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
1766 void ETH_SoftwareReset(void);
1767 FlagStatus ETH_GetSoftwareResetStatus(void);
1768 void ETH_Start(void);
1769 void ETH_Stop(void);
1770 uint32_t ETH_GetRxPktSize(ETH_DMADESCTypeDef *DMARxDesc);
1771 
1772 
1773 #ifdef USE_ENHANCED_DMA_DESCRIPTORS
1774  void ETH_EnhancedDescriptorCmd(FunctionalState NewState);
1775 #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
1776 
1777 /**
1778  * @brief PHY
1779  */
1780 uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg);
1781 uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue);
1782 uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState);
1783 
1784 /**
1785  * @brief MAC
1786  */
1787 void ETH_MACTransmissionCmd(FunctionalState NewState);
1788 void ETH_MACReceptionCmd(FunctionalState NewState);
1789 FlagStatus ETH_GetFlowControlBusyStatus(void);
1790 void ETH_InitiatePauseControlFrame(void);
1791 void ETH_BackPressureActivationCmd(FunctionalState NewState);
1792 FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG);
1793 ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT);
1794 void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState);
1795 void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr);
1796 void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr);
1797 void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState);
1798 void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter);
1799 void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte);
1800 
1801 /**
1802  * @brief DMA Tx/Rx descriptors
1803  */
1804 void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
1805 void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
1806 uint32_t ETH_CheckFrameReceived(void);
1807 uint32_t ETH_Prepare_Transmit_Descriptors(u16 FrameLength);
1808 FrameTypeDef ETH_Get_Received_Frame(void);
1809 FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag);
1810 uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
1811 void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
1812 void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
1813 void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment);
1814 void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);
1815 void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
1816 void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
1817 void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
1818 void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2);
1819 FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag);
1820 #ifdef USE_ENHANCED_DMA_DESCRIPTORS
1821  FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag);
1822 #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
1823 void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
1824 uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
1825 void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
1826 void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
1827 uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer);
1828 FrameTypeDef ETH_Get_Received_Frame_interrupt(void);
1829 /**
1830  * @brief DMA
1831  */
1832 FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG);
1833 void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG);
1834 ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT);
1835 void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT);
1836 uint32_t ETH_GetTransmitProcessState(void);
1837 uint32_t ETH_GetReceiveProcessState(void);
1838 void ETH_FlushTransmitFIFO(void);
1839 FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
1840 void ETH_DMATransmissionCmd(FunctionalState NewState);
1841 void ETH_DMAReceptionCmd(FunctionalState NewState);
1842 void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState);
1843 FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow);
1844 uint32_t ETH_GetRxOverflowMissedFrameCounter(void);
1845 uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);
1846 uint32_t ETH_GetCurrentTxDescStartAddress(void);
1847 uint32_t ETH_GetCurrentRxDescStartAddress(void);
1848 uint32_t ETH_GetCurrentTxBufferAddress(void);
1849 uint32_t ETH_GetCurrentRxBufferAddress(void);
1850 void ETH_ResumeDMATransmission(void);
1851 void ETH_ResumeDMAReception(void);
1852 void ETH_SetReceiveWatchdogTimer(uint8_t Value);
1853 
1854 
1855 /**
1856  * @brief PMT
1857  */
1858 void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
1859 void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer);
1860 void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
1861 FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG);
1862 void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
1863 void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
1864 void ETH_PowerDownCmd(FunctionalState NewState);
1865 
1866 /**
1867  * @brief MMC
1868  */
1869 void ETH_MMCCounterFullPreset(void);
1870 void ETH_MMCCounterHalfPreset(void);
1871 void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
1872 void ETH_MMCResetOnReadCmd(FunctionalState NewState);
1873 void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
1874 void ETH_MMCCountersReset(void);
1875 void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState);
1876 ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT);
1877 uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg);
1878 
1879 #ifdef __cplusplus
1880 }
1881 #endif
1882 
1883 #endif /* __STM32F4x7_ETH_H */
1884 /**
1885  * @}
1886  */
1887 
1888 
1889 /**
1890  * @}
1891  */
1892 
1893 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ETH_InitTypeDef::ETH_DeferralCheck
uint32_t ETH_DeferralCheck
Definition: stm32f4xx_eth.h:108
ETH_InitTypeDef::ETH_PauseTime
uint32_t ETH_PauseTime
Definition: stm32f4xx_eth.h:139
ETH_InitTypeDef::ETH_ReceiveFlowControl
uint32_t ETH_ReceiveFlowControl
Definition: stm32f4xx_eth.h:153
ETH_InitTypeDef::ETH_RxDMABurstLength
uint32_t ETH_RxDMABurstLength
Definition: stm32f4xx_eth.h:206
ETH_DMARxDescChainInit
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
DMA Tx/Rx descriptors.
ETH_InitTypeDef::ETH_AddressAlignedBeats
uint32_t ETH_AddressAlignedBeats
Definition: stm32f4xx_eth.h:200
ETH_InitTypeDef::ETH_MulticastFramesFilter
uint32_t ETH_MulticastFramesFilter
Definition: stm32f4xx_eth.h:129
ETH_InitTypeDef::ETH_CarrierSense
uint32_t ETH_CarrierSense
Definition: stm32f4xx_eth.h:78
ETH_InitTypeDef::ETH_ForwardErrorFrames
uint32_t ETH_ForwardErrorFrames
Definition: stm32f4xx_eth.h:186
ETH_InitTypeDef::ETH_ChecksumOffload
uint32_t ETH_ChecksumOffload
Definition: stm32f4xx_eth.h:95
ETH_InitTypeDef::ETH_ReceiveAll
uint32_t ETH_ReceiveAll
Definition: stm32f4xx_eth.h:111
ETH_InitTypeDef::ETH_VLANTagIdentifier
uint32_t ETH_VLANTagIdentifier
Definition: stm32f4xx_eth.h:165
ETH_InitTypeDef::ETH_TransmitStoreForward
uint32_t ETH_TransmitStoreForward
Definition: stm32f4xx_eth.h:180
ETH_InitTypeDef::ETH_DestinationAddrFilter
uint32_t ETH_DestinationAddrFilter
Definition: stm32f4xx_eth.h:123
ETH_InitTypeDef::ETH_DMAArbitration
uint32_t ETH_DMAArbitration
Definition: stm32f4xx_eth.h:214
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
ETH_InitTypeDef::ETH_ReceiveStoreForward
uint32_t ETH_ReceiveStoreForward
Definition: stm32f4xx_eth.h:174
ETH_InitTypeDef::ETH_PauseLowThreshold
uint32_t ETH_PauseLowThreshold
Definition: stm32f4xx_eth.h:145
ETH_InitTypeDef::ETH_HashTableLow
uint32_t ETH_HashTableLow
Definition: stm32f4xx_eth.h:137
ETH_GetDMAFlagStatus
FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)
DMA.
ETH_InitTypeDef::ETH_SourceAddrFilter
uint32_t ETH_SourceAddrFilter
Definition: stm32f4xx_eth.h:114
ETH_InitTypeDef::ETH_Speed
uint32_t ETH_Speed
Definition: stm32f4xx_eth.h:81
ETH_InitTypeDef::ETH_TxDMABurstLength
uint32_t ETH_TxDMABurstLength
Definition: stm32f4xx_eth.h:209
ETH_InitTypeDef::ETH_UnicastFramesFilter
uint32_t ETH_UnicastFramesFilter
Definition: stm32f4xx_eth.h:132
ETH_InitTypeDef::ETH_SecondFrameOperate
uint32_t ETH_SecondFrameOperate
Definition: stm32f4xx_eth.h:196
ETH_InitTypeDef::ETH_ReceiveOwn
uint32_t ETH_ReceiveOwn
Definition: stm32f4xx_eth.h:84
ETH_DMADESCTypeDef::ControlBufferSize
uint32_t ControlBufferSize
Definition: stm32f4xx_eth.h:229
ETH_InitTypeDef::ETH_BackOffLimit
uint32_t ETH_BackOffLimit
Definition: stm32f4xx_eth.h:105
ETH_MACTransmissionCmd
void ETH_MACTransmissionCmd(FunctionalState NewState)
MAC.
ETH_InitTypeDef::ETH_VLANTagComparison
uint32_t ETH_VLANTagComparison
Definition: stm32f4xx_eth.h:161
ETH_ReadPHYRegister
uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
PHY.
ETH_InitTypeDef
ETH MAC Init structure definition.
Definition: stm32f4xx_eth.h:56
ETH_InitTypeDef::ETH_BroadcastFramesReception
uint32_t ETH_BroadcastFramesReception
Definition: stm32f4xx_eth.h:120
ETH_InitTypeDef::ETH_PassControlFrames
uint32_t ETH_PassControlFrames
Definition: stm32f4xx_eth.h:117
ETH_DMADESCTypeDef
DMA descriptors types.
Definition: stm32f4xx_eth.h:227
ETH_InitTypeDef::ETH_AutoNegotiation
uint32_t ETH_AutoNegotiation
/ * MAC
Definition: stm32f4xx_eth.h:60
ETH_DMADESCTypeDef::Buffer1Addr
uint32_t Buffer1Addr
Definition: stm32f4xx_eth.h:230
ETH_InitTypeDef::ETH_FixedBurst
uint32_t ETH_FixedBurst
Definition: stm32f4xx_eth.h:203
ETH_InitTypeDef::ETH_ReceiveThresholdControl
uint32_t ETH_ReceiveThresholdControl
Definition: stm32f4xx_eth.h:193
ETH_InitTypeDef::ETH_RetryTransmission
uint32_t ETH_RetryTransmission
Definition: stm32f4xx_eth.h:98
ETH_InitTypeDef::ETH_Watchdog
uint32_t ETH_Watchdog
Definition: stm32f4xx_eth.h:65
ETH_DMADESCTypeDef::Buffer2NextDescAddr
uint32_t Buffer2NextDescAddr
Definition: stm32f4xx_eth.h:231
ETH_InitTypeDef::ETH_ForwardUndersizedGoodFrames
uint32_t ETH_ForwardUndersizedGoodFrames
Definition: stm32f4xx_eth.h:189
ETH_DMADESCTypeDef::Status
__IO uint32_t Status
Definition: stm32f4xx_eth.h:228
ETH_InitTypeDef::ETH_TransmitThresholdControl
uint32_t ETH_TransmitThresholdControl
Definition: stm32f4xx_eth.h:183
ETH_InitTypeDef::ETH_Jabber
uint32_t ETH_Jabber
Definition: stm32f4xx_eth.h:70
ETH_InitTypeDef::ETH_LoopbackMode
uint32_t ETH_LoopbackMode
Definition: stm32f4xx_eth.h:89
ETH_InitTypeDef::ETH_PromiscuousMode
uint32_t ETH_PromiscuousMode
Definition: stm32f4xx_eth.h:126
ETH_InitTypeDef::ETH_Mode
uint32_t ETH_Mode
Definition: stm32f4xx_eth.h:92
ETH_InitTypeDef::ETH_InterFrameGap
uint32_t ETH_InterFrameGap
Definition: stm32f4xx_eth.h:75
ETH_InitTypeDef::ETH_ZeroQuantaPause
uint32_t ETH_ZeroQuantaPause
Definition: stm32f4xx_eth.h:142
ETH_InitTypeDef::ETH_AutomaticPadCRCStrip
uint32_t ETH_AutomaticPadCRCStrip
Definition: stm32f4xx_eth.h:102
ETH_InitTypeDef::ETH_UnicastPauseFrameDetect
uint32_t ETH_UnicastPauseFrameDetect
Definition: stm32f4xx_eth.h:149
ETH_InitTypeDef::ETH_TransmitFlowControl
uint32_t ETH_TransmitFlowControl
Definition: stm32f4xx_eth.h:157
ETH_MMCCounterFullPreset
void ETH_MMCCounterFullPreset(void)
MMC.
ETH_ResetWakeUpFrameFilterRegisterPointer
void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
PMT.
ETH_InitTypeDef::ETH_DropTCPIPChecksumErrorFrame
uint32_t ETH_DropTCPIPChecksumErrorFrame
/ * DMA
Definition: stm32f4xx_eth.h:171
ETH_InitTypeDef::ETH_DescriptorSkipLength
uint32_t ETH_DescriptorSkipLength
Definition: stm32f4xx_eth.h:212
ETH_InitTypeDef::ETH_FlushReceivedFrame
uint32_t ETH_FlushReceivedFrame
Definition: stm32f4xx_eth.h:177
ETH_InitTypeDef::ETH_HashTableHigh
uint32_t ETH_HashTableHigh
Definition: stm32f4xx_eth.h:135
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