ENET_Buffers_setting

ETH Frames defines. More...

Collaboration diagram for ENET_Buffers_setting:

Macros
#define	ETH_MAX_PACKET_SIZE
#define	ETH_HEADER
#define	ETH_CRC
#define	ETH_EXTRA
#define	VLAN_TAG
#define	MIN_ETH_PAYLOAD
#define	MAX_ETH_PAYLOAD
#define	JUMBO_FRAME_PAYLOAD
#define	ETH_DMATxDesc_OWN
	Ethernet DMA descriptors registers bits definition. More...
#define	ETH_DMATxDesc_IC
#define	ETH_DMATxDesc_LS
#define	ETH_DMATxDesc_FS
#define	ETH_DMATxDesc_DC
#define	ETH_DMATxDesc_DP
#define	ETH_DMATxDesc_TTSE
#define	ETH_DMATxDesc_CIC
#define	ETH_DMATxDesc_CIC_ByPass
#define	ETH_DMATxDesc_CIC_IPV4Header
#define	ETH_DMATxDesc_CIC_TCPUDPICMP_Segment
#define	ETH_DMATxDesc_CIC_TCPUDPICMP_Full
#define	ETH_DMATxDesc_TER
#define	ETH_DMATxDesc_TCH
#define	ETH_DMATxDesc_TTSS
#define	ETH_DMATxDesc_IHE
#define	ETH_DMATxDesc_ES
#define	ETH_DMATxDesc_JT
#define	ETH_DMATxDesc_FF
#define	ETH_DMATxDesc_PCE
#define	ETH_DMATxDesc_LCA
#define	ETH_DMATxDesc_NC
#define	ETH_DMATxDesc_LCO
#define	ETH_DMATxDesc_EC
#define	ETH_DMATxDesc_VF
#define	ETH_DMATxDesc_CC
#define	ETH_DMATxDesc_ED
#define	ETH_DMATxDesc_UF
#define	ETH_DMATxDesc_DB
#define	ETH_DMATxDesc_TBS2
	Bit definition of TDES1 register. More...
#define	ETH_DMATxDesc_TBS1
#define	ETH_DMATxDesc_B1AP
	Bit definition of TDES2 register. More...
#define	ETH_DMATxDesc_B2AP
	Bit definition of TDES3 register. More...

Detailed Description

ETH Frames defines.

---

--------------------------------------------------------------------——

Macro Definition Documentation

#define ETH_MAX_PACKET_SIZE

ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC

Definition at line 273 of file stm32f4xx_eth.h.

#define ETH_HEADER

6 byte Dest addr, 6 byte Src addr, 2 byte length/type

Definition at line 274 of file stm32f4xx_eth.h.

#define ETH_CRC

Ethernet CRC

Definition at line 275 of file stm32f4xx_eth.h.

#define ETH_EXTRA

Extra bytes in some cases

Definition at line 276 of file stm32f4xx_eth.h.

#define VLAN_TAG

optional 802.1q VLAN Tag

Definition at line 277 of file stm32f4xx_eth.h.

#define MIN_ETH_PAYLOAD

Minimum Ethernet payload size

Definition at line 278 of file stm32f4xx_eth.h.

#define MAX_ETH_PAYLOAD

Maximum Ethernet payload size

Definition at line 279 of file stm32f4xx_eth.h.

#define JUMBO_FRAME_PAYLOAD

Jumbo frame payload size

Definition at line 280 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_OWN

Ethernet DMA descriptors registers bits definition.

---

--------------------------------------------------------------————

 DMA Tx Desciptor
-----------------------------------------------------------------------------------------------
TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
-----------------------------------------------------------------------------------------------
TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
-----------------------------------------------------------------------------------------------
TDES2 |                         Buffer1 Address [31:0]                                         |
-----------------------------------------------------------------------------------------------
TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
-----------------------------------------------------------------------------------------------

Bit definition of TDES0 register: DMA Tx descriptor status registerOWN bit: descriptor is owned by DMA engine

Definition at line 361 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_IC

Interrupt on Completion

Definition at line 362 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_LS

Last Segment

Definition at line 363 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_FS

First Segment

Definition at line 364 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_DC

Disable CRC

Definition at line 365 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_DP

Disable Padding

Definition at line 366 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_TTSE

Transmit Time Stamp Enable

Definition at line 367 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_CIC

Checksum Insertion Control: 4 cases

Definition at line 368 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_CIC_ByPass

Do Nothing: Checksum Engine is bypassed

Definition at line 369 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_CIC_IPV4Header

IPV4 header Checksum Insertion

Definition at line 370 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment

TCP/UDP/ICMP Checksum Insertion calculated over segment only

Definition at line 371 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full

TCP/UDP/ICMP Checksum Insertion fully calculated

Definition at line 372 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_TER

Transmit End of Ring

Definition at line 373 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_TCH

Second Address Chained

Definition at line 374 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_TTSS

Tx Time Stamp Status

Definition at line 375 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_IHE

IP Header Error

Definition at line 376 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_ES

Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT

Definition at line 377 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_JT

Jabber Timeout

Definition at line 378 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_FF

Frame Flushed: DMA/MTL flushed the frame due to SW flush

Definition at line 379 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_PCE

Payload Checksum Error

Definition at line 380 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_LCA

Loss of Carrier: carrier lost during transmission

Definition at line 381 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_NC

No Carrier: no carrier signal from the transceiver

Definition at line 382 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_LCO

Late Collision: transmission aborted due to collision

Definition at line 383 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_EC

Excessive Collision: transmission aborted after 16 collisions

Definition at line 384 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_VF

VLAN Frame

Definition at line 385 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_CC

Collision Count

Definition at line 386 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_ED

Excessive Deferral

Definition at line 387 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_UF

Underflow Error: late data arrival from the memory

Definition at line 388 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_DB

Deferred Bit

Definition at line 389 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_TBS2

Bit definition of TDES1 register.

Transmit Buffer2 Size

Definition at line 394 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_TBS1

Transmit Buffer1 Size

Definition at line 395 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_B1AP

Bit definition of TDES2 register.

Buffer1 Address Pointer

Definition at line 400 of file stm32f4xx_eth.h.

#define ETH_DMATxDesc_B2AP

Bit definition of TDES3 register.

Buffer2 Address Pointer

Definition at line 405 of file stm32f4xx_eth.h.