stm32_usart.c

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/**
 * \file    heivs/stm32_usart.c
 * \brief   usart bus
 * \author  marc dot pignat at hevs dot ch
 */

#include "heivs/stm32_usart.h"
#include "heivs/time.h"
#include "heivs/bsp.h"
#include "stm32/stm32f4xx_usart.h"
#include "stm32/stm32f4xx_rcc.h"

static status_e init(const struct heivs_bus_t *bus)
{
    struct usart_bus_private_t *usart = (struct usart_bus_private_t*)bus->priv;
    USART_InitTypeDef USART_InitStruct;
    status_e status;

    status = gpio_setup_list(usart->gpios, ARRAY_SIZE(usart->gpios));
    if (status != NO_ERROR)
    {
        return status;
    }

    switch ((uint32_t)usart->ctrl)
    {
    case (uint32_t)USART1:
        RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
        RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
        RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
    break;
    case (uint32_t)USART2:
        RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
    break;
    case (uint32_t)USART3:
        RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
    break;
    case (uint32_t)UART4:
        RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);
        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
    break;
    case (uint32_t)UART5:
        RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
    break;
    case (uint32_t)USART6:
        RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
        RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
        RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
    break;
    }

    USART_InitStruct.USART_BaudRate = usart->speed;
    USART_InitStruct.USART_WordLength = USART_WordLength_8b;
    USART_InitStruct.USART_StopBits = USART_StopBits_1;
    USART_InitStruct.USART_Parity = USART_Parity_No;
    USART_InitStruct.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
    USART_InitStruct.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
    USART_Init(usart->ctrl, &USART_InitStruct);
    USART_Cmd(usart->ctrl, ENABLE);

    return NO_ERROR;
}

static status_e suspend(const struct heivs_bus_t *bus)
{
    (void)bus;
    return ERROR_NOT_YET_IMPLEMENTED;
}

static status_e read(const struct heivs_bus_t *bus, uint32_t address, uint8_t *data, size_t len, size_t *rlen)
{
    struct usart_bus_private_t *usart = (struct usart_bus_private_t*)bus->priv;
    size_t i;

    (void)address;

    *rlen = 0;
    for (i = 0 ; i < len ; i++)
    {
        timeout_t timeout = time_set_timeout_ms(100);
        while (!(usart->ctrl->SR & USART_SR_RXNE))
        {
            if (time_elapsed(timeout))
            {
                return ERROR_TIMEOUT;
            }
        }
        data[i] = usart->ctrl->DR;
        *rlen = *rlen + 1;
    }

    return NO_ERROR;
}

static status_e write(const struct heivs_bus_t *bus, uint32_t address, const uint8_t *data, size_t len)
{
    struct usart_bus_private_t *usart = (struct usart_bus_private_t*)bus->priv;

    size_t i;

    (void)address;

    for (i = 0 ; i < len ; i++)
    {
        timeout_t timeout = time_set_timeout_ms((10*1000/usart->speed)+1);
        while (!(usart->ctrl->SR & USART_SR_TC))
        {
            if (time_elapsed(timeout))
            {
                return ERROR_TIMEOUT;
            }
        }
        usart->ctrl->DR = data[i];
    }
    return NO_ERROR;
}

static status_e writeread(const struct heivs_bus_t *bus, uint32_t address, const uint8_t *src, size_t src_len, uint8_t *dst, size_t dst_len, size_t *rlen)
{
    (void)bus;
    (void)address;
    (void)src;
    (void)src_len;
    (void)dst;
    (void)dst_len;
    (void)rlen;
    return ERROR_NOT_SUPPORTED;
}

static const struct usart_bus_private_t bus_priv[BSP_USART_BUS_COUNT] =
{
#if BSP_USART_BUS_COUNT > 0
    {
        .ctrl       = BSP_USART_BUS0_CTRL,
        .gpios      =
        {
            BSP_USART_BUS0_GPIO_TX,
            BSP_USART_BUS0_GPIO_RX,
        },
        .speed      = BSP_USART_BUS0_SPEED,
    },
#endif
#if BSP_USART_BUS_COUNT > 1
    {
        .ctrl       = BSP_USART_BUS1_CTRL,
        .gpios      =
        {
            BSP_USART_BUS1_GPIO_TX,
            BSP_USART_BUS1_GPIO_RX,
        },
        .speed      = BSP_USART_BUS1_SPEED,
    },
#endif
#if BSP_USART_BUS_COUNT > 2
    {
        .ctrl       = BSP_USART_BUS2_CTRL,
        .gpios      =
        {
            BSP_USART_BUS2_GPIO_TX,
            BSP_USART_BUS2_GPIO_RX,
        },
        .speed      = BSP_USART_BUS2_SPEED,
    },
#endif
#if BSP_USART_BUS_COUNT > 3
    {
        .ctrl       = BSP_USART_BUS3_CTRL,
        .gpios      =
        {
            BSP_USART_BUS3_GPIO_TX,
            BSP_USART_BUS3_GPIO_RX,
        },
        .speed      = BSP_USART_BUS3_SPEED,
    },
#endif
#if BSP_USART_BUS_COUNT > 4
    {
        .ctrl       = BSP_USART_BUS4_CTRL,
        .gpios      =
        {
            BSP_USART_BUS4_GPIO_TX,
            BSP_USART_BUS4_GPIO_RX,
        },
        .speed      = BSP_USART_BUS4_SPEED,
    },
#endif
#if BSP_USART_BUS_COUNT > 5
    {
        .ctrl       = BSP_USART_BUS5_CTRL,
        .gpios      =
        {
            BSP_USART_BUS5_GPIO_TX,
            BSP_USART_BUS5_GPIO_RX,
        },
        .speed      = BSP_USART_BUS5_SPEED,
    },
#endif
};

static struct heivs_bus_var_t bus_var[BSP_USART_BUS_COUNT];

const struct heivs_bus_t bus_usart[BSP_USART_BUS_COUNT] =
{
    #ifndef BSP_USART_BUS0_NAME
        #define BSP_USART_BUS0_NAME "bus_usart[0]"
    #endif
#if BSP_USART_BUS_COUNT > 0
    {
        .name = BSP_USART_BUS0_NAME,
        .priv = &bus_priv[0],
        .var = &bus_var[0],

        ._init = init,
        ._read = read,
        ._write = write,
        ._suspend = suspend,
        ._writeread = writeread,
    },
#endif
#if BSP_USART_BUS_COUNT > 1
    #ifndef BSP_USART_BUS1_NAME
        #define BSP_USART_BUS1_NAME "bus_usart[1]"
    #endif
    {
        .name = BSP_USART_BUS1_NAME,
        .priv = &bus_priv[1],
        .var = &bus_var[1],

        ._init = init,
        ._read = read,
        ._write = write,
        ._suspend = suspend,
        ._writeread = writeread,
    },
#endif
#if BSP_USART_BUS_COUNT > 2
    #ifndef BSP_USART_BUS2_NAME
        #define BSP_USART_BUS2_NAME "bus_usart[2]"
    #endif
    {
        .name = BSP_USART_BUS2_NAME,
        .priv = &bus_priv[2],
        .var = &bus_var[2],

        ._init = init,
        ._read = read,
        ._write = write,
        ._suspend = suspend,
        ._writeread = writeread,
    },
#endif
#if BSP_USART_BUS_COUNT > 3
    #ifndef BSP_USART_BUS3_NAME
        #define BSP_USART_BUS3_NAME "bus_usart[3]"
    #endif
    {
        .name = BSP_USART_BUS3_NAME,
        .priv = &bus_priv[3],
        .var = &bus_var[3],

        ._init = init,
        ._read = read,
        ._write = write,
        ._suspend = suspend,
        ._writeread = writeread,
    },
#endif
#if BSP_USART_BUS_COUNT > 4
    #ifndef BSP_USART_BUS4_NAME
        #define BSP_USART_BUS4_NAME "bus_usart[4]"
    #endif
    {
        .name = BSP_USART_BUS4_NAME,
        .priv = &bus_priv[4],
        .var = &bus_var[4],

        ._init = init,
        ._read = read,
        ._write = write,
        ._suspend = suspend,
        ._writeread = writeread,
    },
#endif
#if BSP_USART_BUS_COUNT > 5
    #ifndef BSP_USART_BUS5_NAME
        #define BSP_USART_BUS5_NAME "bus_usart[5]"
    #endif
    {
        .name = BSP_USART_BUS5_NAME,
        .priv = &bus_priv[5],
        .var = &bus_var[5],

        .init = init,
        ._read = read,
        ._write = write,
        ._suspend = suspend,
        ._writeread = writeread,
    },
#endif
#if BSP_USART_BUS_COUNT > 6
    #error this CPU has no 7 usart buses
#endif
};