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stm32f4xx_flash.h
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1 /**
2  ******************************************************************************
3  * @file stm32f4xx_flash.h
4  * @author MCD Application Team
5  * @version V1.0.0
6  * @date 30-September-2011
7  * @brief This file contains all the functions prototypes for the FLASH
8  * firmware library.
9  ******************************************************************************
10  * @attention
11  *
12  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18  *
19  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
20  ******************************************************************************
21  */
22 
23 /* Define to prevent recursive inclusion -------------------------------------*/
24 #ifndef __STM32F4xx_FLASH_H
25 #define __STM32F4xx_FLASH_H
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 /* Includes ------------------------------------------------------------------*/
32 #include "stm32/stm32f4xx.h"
33 
34 /** @addtogroup STM32F4xx_StdPeriph_Driver
35  * @{
36  */
37 
38 /** @addtogroup FLASH
39  * @{
40  */
41 
42 /* Exported types ------------------------------------------------------------*/
43 /**
44  * @brief FLASH Status
45  */
46 typedef enum
47 {
48  FLASH_BUSY = 1,
49  FLASH_ERROR_PGS,
50  FLASH_ERROR_PGP,
51  FLASH_ERROR_PGA,
52  FLASH_ERROR_WRP,
53  FLASH_ERROR_PROGRAM,
54  FLASH_ERROR_OPERATION,
55  FLASH_COMPLETE
56 }FLASH_Status;
57 
58 /* Exported constants --------------------------------------------------------*/
59 
60 /** @defgroup FLASH_Exported_Constants
61  * @{
62  */
63 
64 /** @defgroup Flash_Latency
65  * @{
66  */
67 #define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
68 #define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */
69 #define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */
70 #define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */
71 #define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */
72 #define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */
73 #define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */
74 #define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */
75 
76 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
77  ((LATENCY) == FLASH_Latency_1) || \
78  ((LATENCY) == FLASH_Latency_2) || \
79  ((LATENCY) == FLASH_Latency_3) || \
80  ((LATENCY) == FLASH_Latency_4) || \
81  ((LATENCY) == FLASH_Latency_5) || \
82  ((LATENCY) == FLASH_Latency_6) || \
83  ((LATENCY) == FLASH_Latency_7))
84 /**
85  * @}
86  */
87 
88 /** @defgroup FLASH_Voltage_Range
89  * @{
90  */
91 #define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
92 #define VoltageRange_2 ((uint8_t)0x01) /*!<Device operating range: 2.1V to 2.7V */
93 #define VoltageRange_3 ((uint8_t)0x02) /*!<Device operating range: 2.7V to 3.6V */
94 #define VoltageRange_4 ((uint8_t)0x03) /*!<Device operating range: 2.7V to 3.6V + External Vpp */
95 
96 #define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
97  ((RANGE) == VoltageRange_2) || \
98  ((RANGE) == VoltageRange_3) || \
99  ((RANGE) == VoltageRange_4))
100 /**
101  * @}
102  */
103 
104 /** @defgroup FLASH_Sectors
105  * @{
106  */
107 #define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */
108 #define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */
109 #define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */
110 #define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */
111 #define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */
112 #define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */
113 #define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */
114 #define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */
115 #define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */
116 #define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */
117 #define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */
118 #define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */
119 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\
120  ((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\
121  ((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\
122  ((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\
123  ((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\
124  ((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11))
125 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
126  (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
127 /**
128  * @}
129  */
130 
131 /** @defgroup Option_Bytes_Write_Protection
132  * @{
133  */
134 #define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
135 #define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
136 #define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
137 #define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
138 #define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
139 #define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
140 #define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
141 #define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
142 #define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
143 #define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
144 #define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
145 #define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
146 #define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
147 
148 #define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
149 /**
150  * @}
151  */
152 
153 /** @defgroup FLASH_Option_Bytes_Read_Protection
154  * @{
155  */
156 #define OB_RDP_Level_0 ((uint8_t)0xAA)
157 #define OB_RDP_Level_1 ((uint8_t)0x55)
158 /*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
159  it's no more possible to go back to level 1 or 0 */
160 #define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
161  ((LEVEL) == OB_RDP_Level_1))/*||\
162  ((LEVEL) == OB_RDP_Level_2))*/
163 /**
164  * @}
165  */
166 
167 /** @defgroup FLASH_Option_Bytes_IWatchdog
168  * @{
169  */
170 #define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
171 #define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
172 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
173 /**
174  * @}
175  */
176 
177 /** @defgroup FLASH_Option_Bytes_nRST_STOP
178  * @{
179  */
180 #define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
181 #define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
182 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
183 /**
184  * @}
185  */
186 
187 
188 /** @defgroup FLASH_Option_Bytes_nRST_STDBY
189  * @{
190  */
191 #define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
192 #define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
193 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
194 /**
195  * @}
196  */
197 
198 /** @defgroup FLASH_BOR_Reset_Level
199  * @{
200  */
201 #define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
202 #define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
203 #define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
204 #define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
205 #define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
206  ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
207 /**
208  * @}
209  */
210 
211 /** @defgroup FLASH_Interrupts
212  * @{
213  */
214 #define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */
215 #define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */
216 #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
217 /**
218  * @}
219  */
220 
221 /** @defgroup FLASH_Flags
222  * @{
223  */
224 #define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */
225 #define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */
226 #define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
227 #define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */
228 #define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */
229 #define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */
230 #define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */
231 #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000))
232 #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
233  ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
234  ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
235  ((FLAG) == FLASH_FLAG_BSY))
236 /**
237  * @}
238  */
239 
240 /** @defgroup FLASH_Program_Parallelism
241  * @{
242  */
243 #define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
244 #define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100)
245 #define FLASH_PSIZE_WORD ((uint32_t)0x00000200)
246 #define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300)
247 #define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)
248 /**
249  * @}
250  */
251 
252 /** @defgroup FLASH_Keys
253  * @{
254  */
255 #define RDP_KEY ((uint16_t)0x00A5)
256 #define FLASH_KEY1 ((uint32_t)0x45670123)
257 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
258 #define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
259 #define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)
260 /**
261  * @}
262  */
263 
264 /**
265  * @brief ACR register byte 0 (Bits[8:0]) base address
266  */
267 #define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
268 /**
269  * @brief OPTCR register byte 3 (Bits[24:16]) base address
270  */
271 #define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
272 #define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
273 #define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
274 
275 /**
276  * @}
277  */
278 
279 /* Exported macro ------------------------------------------------------------*/
280 /* Exported functions --------------------------------------------------------*/
281 
282 /* FLASH Interface configuration functions ************************************/
283 void FLASH_SetLatency(uint32_t FLASH_Latency);
284 void FLASH_PrefetchBufferCmd(FunctionalState NewState);
285 void FLASH_InstructionCacheCmd(FunctionalState NewState);
286 void FLASH_DataCacheCmd(FunctionalState NewState);
287 void FLASH_InstructionCacheReset(void);
288 void FLASH_DataCacheReset(void);
289 
290 /* FLASH Memory Programming functions *****************************************/
291 void FLASH_Unlock(void);
292 void FLASH_Lock(void);
293 FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
294 FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
295 FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
296 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
297 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
298 FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
299 
300 /* Option Bytes Programming functions *****************************************/
301 void FLASH_OB_Unlock(void);
302 void FLASH_OB_Lock(void);
303 void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
304 void FLASH_OB_RDPConfig(uint8_t OB_RDP);
305 void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
306 void FLASH_OB_BORConfig(uint8_t OB_BOR);
307 FLASH_Status FLASH_OB_Launch(void);
308 uint8_t FLASH_OB_GetUser(void);
309 uint16_t FLASH_OB_GetWRP(void);
310 FlagStatus FLASH_OB_GetRDP(void);
311 uint8_t FLASH_OB_GetBOR(void);
312 
313 /* Interrupts and flags management functions **********************************/
314 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
315 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
316 void FLASH_ClearFlag(uint32_t FLASH_FLAG);
317 FLASH_Status FLASH_GetStatus(void);
318 FLASH_Status FLASH_WaitForLastOperation(void);
319 
320 #ifdef __cplusplus
321 }
322 #endif
323 
324 #endif /* __STM32F4xx_FLASH_H */
325 
326 /**
327  * @}
328  */
329 
330 /**
331  * @}
332  */
333 
334 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
FLASH_Status
FLASH_Status
FLASH Status.
Definition: stm32f4xx_flash.h:46
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