stm32_spi.c

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/**
 * \file    heivs/stm32_spi.c
 * \brief   spi bus
 * \author  marc dot pignat at hevs dot ch
 ***************************************************************************/

#include "heivs/stm32_spi.h"
#include "heivs/time.h"
#include "heivs/bsp.h"
#include "stm32/stm32f4xx_spi.h"
#include "stm32/stm32f4xx_rcc.h"

#define SPI_STD_TIMEOUT_MS 10

static status_e init(const struct heivs_bus_t *bus)
{
    status_e status;
    const struct spi_bus_private_t *spi = bus->priv;
    SPI_InitTypeDef SPI_InitStruct;

    /* FIXME handle those cases */
    if (spi->options & SPI_OPTION_SLAVE)
    {
        return ERROR_NOT_YET_IMPLEMENTED;
    }

    /* Setup gpios */
    status = gpio_setup_list(spi->gpios, ARRAY_SIZE(spi->gpios));
    if (status != NO_ERROR)
    {
        return status;
    }

    /* Enable the spi controller */
    switch ((uint32_t)spi->ctrl)
        {
        case (uint32_t)SPI1:
            RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
        break;

        case (uint32_t)SPI2:
            RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
        break;

        case (uint32_t)SPI3:
            RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
        break;

        default:
        case 0:
            return ERROR_BAD_PARAM;
        }

    SPI_InitStruct.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
    SPI_InitStruct.SPI_Mode = SPI_Mode_Master;
    SPI_InitStruct.SPI_DataSize = SPI_DataSize_8b;
    switch (spi->options & SPI_OPTION_MODE_3)
    {
    case SPI_OPTION_MODE_0:
        SPI_InitStruct.SPI_CPOL = SPI_CPOL_Low;
        SPI_InitStruct.SPI_CPHA = SPI_CPHA_1Edge;
    break;
    case SPI_OPTION_MODE_1:
        SPI_InitStruct.SPI_CPOL = SPI_CPOL_Low;
        SPI_InitStruct.SPI_CPHA = SPI_CPHA_2Edge;
    break;
    case SPI_OPTION_MODE_2:
        SPI_InitStruct.SPI_CPOL = SPI_CPOL_High;
        SPI_InitStruct.SPI_CPHA = SPI_CPHA_1Edge;
    break;
    case SPI_OPTION_MODE_3:
        SPI_InitStruct.SPI_CPOL = SPI_CPOL_High;
        SPI_InitStruct.SPI_CPHA = SPI_CPHA_2Edge;
    break;
    }

    SPI_InitStruct.SPI_NSS = SPI_NSS_Soft | SPI_NSSInternalSoft_Set;
    SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
    SPI_InitStruct.SPI_FirstBit = SPI_FirstBit_MSB;
    SPI_Init(spi->ctrl, &SPI_InitStruct);

    SPI_Cmd(spi->ctrl, ENABLE);

    return NO_ERROR;
}

static status_e suspend(const struct heivs_bus_t *bus)
{
    (void)bus;
    return ERROR_NOT_YET_IMPLEMENTED;
}

static status_e write_read_one(const struct spi_bus_private_t *spi, const uint8_t *src, uint8_t *dst)
{
    timeout_t timeout = time_set_timeout_ms(SPI_STD_TIMEOUT_MS);

    /* Send one byte */
    spi->ctrl->DR = *src;

    /* Wait for TX empty */
    while (!(spi->ctrl->SR & SPI_I2S_FLAG_TXE))
    {
        if (time_elapsed(timeout))
        {
            return ERROR_TIMEOUT;
        }
    }

    /* Wait for RX finished */
    while (!(spi->ctrl->SR & SPI_I2S_FLAG_RXNE))
    {
        if (time_elapsed(timeout))
        {
            return ERROR_TIMEOUT;
        }
    }

    /* Wait for not busy */
    while (spi->ctrl->SR & SPI_I2S_FLAG_BSY)
    {
        if (time_elapsed(timeout))
        {
            return ERROR_TIMEOUT;
        }
    }

    /* Write back the received value */
    *dst = spi->ctrl->DR;

    return NO_ERROR;
}

static status_e writeread(const struct heivs_bus_t *bus, uint32_t address, const uint8_t *src, size_t src_len, uint8_t *dst, size_t dst_len, size_t *rlen)
{
    const struct spi_bus_private_t *spi = bus->priv;
    size_t i;
    status_e status = NO_ERROR;

    (void)address;

    /* Chip select */
    gpio_set(&spi->gpios[3], spi->options & SPI_OPTION_CS_HIGH);

    /**
     * Do as many access as max(src_len, dst_len)
     */
    for (i = 0 ; i < max(src_len, dst_len) ; i++)
    {
        /* Write to/from this dummy byte when dst_len != src_len */
        uint8_t dummy = 0xff;
        const uint8_t *l_src = &dummy;
        uint8_t *l_dst = &dummy;

        /* Limit src access to src_len*/
        if (i < src_len)
        {
            l_src = &src[i];
        }

        /* Limit dst access to dst_len */
        if (i < dst_len)
        {
            l_dst = &dst[i];
        }

        /* Do one access */
        status = write_read_one(spi, l_src, l_dst);
        if (status != NO_ERROR)
        {
            goto error;
        }

        if (i < dst_len)
        {
            *rlen = *rlen+1;
        }
    }

error:
    /* Chip deselect */
    gpio_set(&spi->gpios[3], !(spi->options & SPI_OPTION_CS_HIGH));

    return status;
}

static status_e read(const struct heivs_bus_t *bus, uint32_t address, uint8_t *data, size_t len, size_t *rlen)
{
    size_t dont_care;
    (void)address;
    (void)rlen;
    return writeread(bus, 0, NULL, 0, data, len, &dont_care);
}

static status_e write(const struct heivs_bus_t *bus, uint32_t address, const uint8_t *data, size_t len)
{
    size_t dont_care;
    (void)address;
    return writeread(bus, 0, data, len, NULL, 0, &dont_care);
}

static const struct spi_bus_private_t bus_priv[BSP_SPI_BUS_COUNT] =
{
#if BSP_SPI_BUS_COUNT > 0
    {
        .ctrl       = BSP_SPI_BUS0_CTRL,
        .options    = SPI_OPTION_MASTER | SPI_OPTION_MODE_0 | SPI_OPTION_CS_LOW,
        .gpios      =
        {
            BSP_SPI_BUS0_GPIO_MISO,
            BSP_SPI_BUS0_GPIO_MOSI,
            BSP_SPI_BUS0_GPIO_SCK,
            BSP_SPI_BUS0_GPIO_CS,
        },
    },
#endif
#if BSP_SPI_BUS_COUNT > 1
    {
        .ctrl       = BSP_SPI_BUS1_CTRL,
        .options    = SPI_OPTION_MASTER | SPI_OPTION_MODE_0 | SPI_OPTION_CS_LOW,
        .gpios      =
        {
            BSP_SPI_BUS1_GPIO_MISO,
            BSP_SPI_BUS1_GPIO_MOSI,
            BSP_SPI_BUS1_GPIO_SCK,
            BSP_SPI_BUS1_GPIO_CS,
        },
    },
#endif
#if BSP_SPI_BUS_COUNT > 2
    {
        .ctrl       = BSP_SPI_BUS2_CTRL,
        .options    = SPI_OPTION_MASTER | SPI_OPTION_MODE_0 | SPI_OPTION_CS_LOW,
        .gpios      =
        {
            BSP_SPI_BUS2_GPIO_MISO,
            BSP_SPI_BUS2_GPIO_MOSI,
            BSP_SPI_BUS2_GPIO_SCK,
            BSP_SPI_BUS2_GPIO_CS,
        },
    },
#endif
};

static struct heivs_bus_var_t bus_var[BSP_SPI_BUS_COUNT];

const struct heivs_bus_t bus_spi[BSP_SPI_BUS_COUNT] =
{
#if BSP_SPI_BUS_COUNT > 0
    #ifndef BSP_SPI_BUS0_NAME
        #define BSP_SPI_BUS0_NAME "bus_spi[0]"
    #endif
    {
        .name = BSP_SPI_BUS0_NAME,
        .priv = &bus_priv[0],
        .var = &bus_var[0],

        ._init = init,
        ._read = read,
        ._write = write,
        ._suspend = suspend,
        ._writeread = writeread,
    },
#endif
#if BSP_SPI_BUS_COUNT > 1
    #ifndef BSP_SPI_BUS1_NAME
        #define BSP_SPI_BUS1_NAME "bus_spi[1]"
    #endif
    {
        .name = BSP_SPI_BUS1_NAME,
        .priv = &bus_priv[1],
        .var = &bus_var[1],

        ._init = init,
        ._read = read,
        ._write = write,
        ._suspend = suspend,
        ._writeread = writeread,
    },
#endif
#if BSP_SPI_BUS_COUNT > 2
    #ifndef BSP_SPI_BUS2_NAME
        #define BSP_SPI_BUS2_NAME "bus_spi[2]"
    #endif
    {
        .name = BSP_SPI_BUS2_NAME,
        .priv = &bus_priv[2],
        .var = &bus_var[2],

        ._init = init,
        ._read = read,
        ._write = write,
        ._suspend = suspend,
        ._writeread = writeread,
    },
#endif
#if BSP_I2C_BUS_COUNT > 3
    #error this CPU has no 4 SPI buses
#endif
};