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stm32f4xx_dma.h
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1 /**
2  ******************************************************************************
3  * @file stm32f4xx_dma.h
4  * @author MCD Application Team
5  * @version V1.0.0
6  * @date 30-September-2011
7  * @brief This file contains all the functions prototypes for the DMA firmware
8  * library.
9  ******************************************************************************
10  * @attention
11  *
12  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18  *
19  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
20  ******************************************************************************
21  */
22 
23 /* Define to prevent recursive inclusion -------------------------------------*/
24 #ifndef __STM32F4xx_DMA_H
25 #define __STM32F4xx_DMA_H
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 /* Includes ------------------------------------------------------------------*/
32 #include "stm32/stm32f4xx.h"
33 
34 /** @addtogroup STM32F4xx_StdPeriph_Driver
35  * @{
36  */
37 
38 /** @addtogroup DMA
39  * @{
40  */
41 
42 /* Exported types ------------------------------------------------------------*/
43 
44 /**
45  * @brief DMA Init structure definition
46  */
47 
48 typedef struct
49 {
50  uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream.
51  This parameter can be a value of @ref DMA_channel */
52 
53  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
54 
55  uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx.
56  This memory is the default memory used when double buffer mode is
57  not enabled. */
58 
59  uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral,
60  from memory to memory or from peripheral to memory.
61  This parameter can be a value of @ref DMA_data_transfer_direction */
62 
63  uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream.
64  The data unit is equal to the configuration set in DMA_PeripheralDataSize
65  or DMA_MemoryDataSize members depending in the transfer direction. */
66 
67  uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
68  This parameter can be a value of @ref DMA_peripheral_incremented_mode */
69 
70  uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.
71  This parameter can be a value of @ref DMA_memory_incremented_mode */
72 
73  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
74  This parameter can be a value of @ref DMA_peripheral_data_size */
75 
76  uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
77  This parameter can be a value of @ref DMA_memory_data_size */
78 
79  uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.
80  This parameter can be a value of @ref DMA_circular_normal_mode
81  @note The circular buffer mode cannot be used if the memory-to-memory
82  data transfer is configured on the selected Stream */
83 
84  uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.
85  This parameter can be a value of @ref DMA_priority_level */
86 
87  uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
88  This parameter can be a value of @ref DMA_fifo_direct_mode
89  @note The Direct mode (FIFO mode disabled) cannot be used if the
90  memory-to-memory data transfer is configured on the selected Stream */
91 
92  uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.
93  This parameter can be a value of @ref DMA_fifo_threshold_level */
94 
95  uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
96  It specifies the amount of data to be transferred in a single non interruptable
97  transaction. This parameter can be a value of @ref DMA_memory_burst
98  @note The burst mode is possible only if the address Increment mode is enabled. */
99 
100  uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
101  It specifies the amount of data to be transferred in a single non interruptable
102  transaction. This parameter can be a value of @ref DMA_peripheral_burst
103  @note The burst mode is possible only if the address Increment mode is enabled. */
104 }DMA_InitTypeDef;
105 
106 /* Exported constants --------------------------------------------------------*/
107 
108 /** @defgroup DMA_Exported_Constants
109  * @{
110  */
111 
112 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
113  ((PERIPH) == DMA1_Stream1) || \
114  ((PERIPH) == DMA1_Stream2) || \
115  ((PERIPH) == DMA1_Stream3) || \
116  ((PERIPH) == DMA1_Stream4) || \
117  ((PERIPH) == DMA1_Stream5) || \
118  ((PERIPH) == DMA1_Stream6) || \
119  ((PERIPH) == DMA1_Stream7) || \
120  ((PERIPH) == DMA2_Stream0) || \
121  ((PERIPH) == DMA2_Stream1) || \
122  ((PERIPH) == DMA2_Stream2) || \
123  ((PERIPH) == DMA2_Stream3) || \
124  ((PERIPH) == DMA2_Stream4) || \
125  ((PERIPH) == DMA2_Stream5) || \
126  ((PERIPH) == DMA2_Stream6) || \
127  ((PERIPH) == DMA2_Stream7))
128 
129 #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
130  ((CONTROLLER) == DMA2))
131 
132 /** @defgroup DMA_channel
133  * @{
134  */
135 #define DMA_Channel_0 ((uint32_t)0x00000000)
136 #define DMA_Channel_1 ((uint32_t)0x02000000)
137 #define DMA_Channel_2 ((uint32_t)0x04000000)
138 #define DMA_Channel_3 ((uint32_t)0x06000000)
139 #define DMA_Channel_4 ((uint32_t)0x08000000)
140 #define DMA_Channel_5 ((uint32_t)0x0A000000)
141 #define DMA_Channel_6 ((uint32_t)0x0C000000)
142 #define DMA_Channel_7 ((uint32_t)0x0E000000)
143 
144 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
145  ((CHANNEL) == DMA_Channel_1) || \
146  ((CHANNEL) == DMA_Channel_2) || \
147  ((CHANNEL) == DMA_Channel_3) || \
148  ((CHANNEL) == DMA_Channel_4) || \
149  ((CHANNEL) == DMA_Channel_5) || \
150  ((CHANNEL) == DMA_Channel_6) || \
151  ((CHANNEL) == DMA_Channel_7))
152 /**
153  * @}
154  */
155 
156 
157 /** @defgroup DMA_data_transfer_direction
158  * @{
159  */
160 #define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)
161 #define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040)
162 #define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)
163 
164 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
165  ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \
166  ((DIRECTION) == DMA_DIR_MemoryToMemory))
167 /**
168  * @}
169  */
170 
171 
172 /** @defgroup DMA_data_buffer_size
173  * @{
174  */
175 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
176 /**
177  * @}
178  */
179 
180 
181 /** @defgroup DMA_peripheral_incremented_mode
182  * @{
183  */
184 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000200)
185 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
186 
187 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
188  ((STATE) == DMA_PeripheralInc_Disable))
189 /**
190  * @}
191  */
192 
193 
194 /** @defgroup DMA_memory_incremented_mode
195  * @{
196  */
197 #define DMA_MemoryInc_Enable ((uint32_t)0x00000400)
198 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
199 
200 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
201  ((STATE) == DMA_MemoryInc_Disable))
202 /**
203  * @}
204  */
205 
206 
207 /** @defgroup DMA_peripheral_data_size
208  * @{
209  */
210 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
211 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800)
212 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)
213 
214 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
215  ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
216  ((SIZE) == DMA_PeripheralDataSize_Word))
217 /**
218  * @}
219  */
220 
221 
222 /** @defgroup DMA_memory_data_size
223  * @{
224  */
225 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
226 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000)
227 #define DMA_MemoryDataSize_Word ((uint32_t)0x00004000)
228 
229 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
230  ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
231  ((SIZE) == DMA_MemoryDataSize_Word ))
232 /**
233  * @}
234  */
235 
236 
237 /** @defgroup DMA_circular_normal_mode
238  * @{
239  */
240 #define DMA_Mode_Normal ((uint32_t)0x00000000)
241 #define DMA_Mode_Circular ((uint32_t)0x00000100)
242 
243 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
244  ((MODE) == DMA_Mode_Circular))
245 /**
246  * @}
247  */
248 
249 
250 /** @defgroup DMA_priority_level
251  * @{
252  */
253 #define DMA_Priority_Low ((uint32_t)0x00000000)
254 #define DMA_Priority_Medium ((uint32_t)0x00010000)
255 #define DMA_Priority_High ((uint32_t)0x00020000)
256 #define DMA_Priority_VeryHigh ((uint32_t)0x00030000)
257 
258 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \
259  ((PRIORITY) == DMA_Priority_Medium) || \
260  ((PRIORITY) == DMA_Priority_High) || \
261  ((PRIORITY) == DMA_Priority_VeryHigh))
262 /**
263  * @}
264  */
265 
266 
267 /** @defgroup DMA_fifo_direct_mode
268  * @{
269  */
270 #define DMA_FIFOMode_Disable ((uint32_t)0x00000000)
271 #define DMA_FIFOMode_Enable ((uint32_t)0x00000004)
272 
273 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
274  ((STATE) == DMA_FIFOMode_Enable))
275 /**
276  * @}
277  */
278 
279 
280 /** @defgroup DMA_fifo_threshold_level
281  * @{
282  */
283 #define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)
284 #define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001)
285 #define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)
286 #define DMA_FIFOThreshold_Full ((uint32_t)0x00000003)
287 
288 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
289  ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \
290  ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
291  ((THRESHOLD) == DMA_FIFOThreshold_Full))
292 /**
293  * @}
294  */
295 
296 
297 /** @defgroup DMA_memory_burst
298  * @{
299  */
300 #define DMA_MemoryBurst_Single ((uint32_t)0x00000000)
301 #define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000)
302 #define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000)
303 #define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)
304 
305 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
306  ((BURST) == DMA_MemoryBurst_INC4) || \
307  ((BURST) == DMA_MemoryBurst_INC8) || \
308  ((BURST) == DMA_MemoryBurst_INC16))
309 /**
310  * @}
311  */
312 
313 
314 /** @defgroup DMA_peripheral_burst
315  * @{
316  */
317 #define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)
318 #define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000)
319 #define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)
320 #define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)
321 
322 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
323  ((BURST) == DMA_PeripheralBurst_INC4) || \
324  ((BURST) == DMA_PeripheralBurst_INC8) || \
325  ((BURST) == DMA_PeripheralBurst_INC16))
326 /**
327  * @}
328  */
329 
330 
331 /** @defgroup DMA_fifo_status_level
332  * @{
333  */
334 #define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)
335 #define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)
336 #define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3)
337 #define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)
338 #define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)
339 #define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)
340 
341 #define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
342  ((STATUS) == DMA_FIFOStatus_HalfFull) || \
343  ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \
344  ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \
345  ((STATUS) == DMA_FIFOStatus_Full) || \
346  ((STATUS) == DMA_FIFOStatus_Empty))
347 /**
348  * @}
349  */
350 
351 /** @defgroup DMA_flags_definition
352  * @{
353  */
354 #define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)
355 #define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)
356 #define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)
357 #define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)
358 #define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)
359 #define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)
360 #define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)
361 #define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)
362 #define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)
363 #define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)
364 #define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)
365 #define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)
366 #define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)
367 #define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)
368 #define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)
369 #define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)
370 #define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)
371 #define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)
372 #define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)
373 #define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)
374 #define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)
375 #define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)
376 #define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)
377 #define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)
378 #define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)
379 #define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)
380 #define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)
381 #define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)
382 #define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)
383 #define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)
384 #define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)
385 #define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)
386 #define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)
387 #define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)
388 #define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)
389 #define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)
390 #define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)
391 #define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)
392 #define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)
393 #define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
394 
395 #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
396  (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00))
397 
398 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
399  ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
400  ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \
401  ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \
402  ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \
403  ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \
404  ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \
405  ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \
406  ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \
407  ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \
408  ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \
409  ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \
410  ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \
411  ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \
412  ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \
413  ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \
414  ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \
415  ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \
416  ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \
417  ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
418 /**
419  * @}
420  */
421 
422 
423 /** @defgroup DMA_interrupt_enable_definitions
424  * @{
425  */
426 #define DMA_IT_TC ((uint32_t)0x00000010)
427 #define DMA_IT_HT ((uint32_t)0x00000008)
428 #define DMA_IT_TE ((uint32_t)0x00000004)
429 #define DMA_IT_DME ((uint32_t)0x00000002)
430 #define DMA_IT_FE ((uint32_t)0x00000080)
431 
432 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
433 /**
434  * @}
435  */
436 
437 
438 /** @defgroup DMA_interrupts_definitions
439  * @{
440  */
441 #define DMA_IT_FEIF0 ((uint32_t)0x90000001)
442 #define DMA_IT_DMEIF0 ((uint32_t)0x10001004)
443 #define DMA_IT_TEIF0 ((uint32_t)0x10002008)
444 #define DMA_IT_HTIF0 ((uint32_t)0x10004010)
445 #define DMA_IT_TCIF0 ((uint32_t)0x10008020)
446 #define DMA_IT_FEIF1 ((uint32_t)0x90000040)
447 #define DMA_IT_DMEIF1 ((uint32_t)0x10001100)
448 #define DMA_IT_TEIF1 ((uint32_t)0x10002200)
449 #define DMA_IT_HTIF1 ((uint32_t)0x10004400)
450 #define DMA_IT_TCIF1 ((uint32_t)0x10008800)
451 #define DMA_IT_FEIF2 ((uint32_t)0x90010000)
452 #define DMA_IT_DMEIF2 ((uint32_t)0x10041000)
453 #define DMA_IT_TEIF2 ((uint32_t)0x10082000)
454 #define DMA_IT_HTIF2 ((uint32_t)0x10104000)
455 #define DMA_IT_TCIF2 ((uint32_t)0x10208000)
456 #define DMA_IT_FEIF3 ((uint32_t)0x90400000)
457 #define DMA_IT_DMEIF3 ((uint32_t)0x11001000)
458 #define DMA_IT_TEIF3 ((uint32_t)0x12002000)
459 #define DMA_IT_HTIF3 ((uint32_t)0x14004000)
460 #define DMA_IT_TCIF3 ((uint32_t)0x18008000)
461 #define DMA_IT_FEIF4 ((uint32_t)0xA0000001)
462 #define DMA_IT_DMEIF4 ((uint32_t)0x20001004)
463 #define DMA_IT_TEIF4 ((uint32_t)0x20002008)
464 #define DMA_IT_HTIF4 ((uint32_t)0x20004010)
465 #define DMA_IT_TCIF4 ((uint32_t)0x20008020)
466 #define DMA_IT_FEIF5 ((uint32_t)0xA0000040)
467 #define DMA_IT_DMEIF5 ((uint32_t)0x20001100)
468 #define DMA_IT_TEIF5 ((uint32_t)0x20002200)
469 #define DMA_IT_HTIF5 ((uint32_t)0x20004400)
470 #define DMA_IT_TCIF5 ((uint32_t)0x20008800)
471 #define DMA_IT_FEIF6 ((uint32_t)0xA0010000)
472 #define DMA_IT_DMEIF6 ((uint32_t)0x20041000)
473 #define DMA_IT_TEIF6 ((uint32_t)0x20082000)
474 #define DMA_IT_HTIF6 ((uint32_t)0x20104000)
475 #define DMA_IT_TCIF6 ((uint32_t)0x20208000)
476 #define DMA_IT_FEIF7 ((uint32_t)0xA0400000)
477 #define DMA_IT_DMEIF7 ((uint32_t)0x21001000)
478 #define DMA_IT_TEIF7 ((uint32_t)0x22002000)
479 #define DMA_IT_HTIF7 ((uint32_t)0x24004000)
480 #define DMA_IT_TCIF7 ((uint32_t)0x28008000)
481 
482 #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
483  (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
484  (((IT) & 0x40820082) == 0x00))
485 
486 #define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
487  ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
488  ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \
489  ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \
490  ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \
491  ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \
492  ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
493  ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \
494  ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \
495  ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \
496  ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \
497  ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
498  ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \
499  ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \
500  ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \
501  ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \
502  ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
503  ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \
504  ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \
505  ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
506 /**
507  * @}
508  */
509 
510 #define DMA_MAX_XFER_COUNT 0xffff
511 
512 /** @defgroup DMA_peripheral_increment_offset
513  * @{
514  */
515 #define DMA_PINCOS_Psize ((uint32_t)0x00000000)
516 #define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)
517 
518 #define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
519  ((SIZE) == DMA_PINCOS_WordAligned))
520 /**
521  * @}
522  */
523 
524 
525 /** @defgroup DMA_flow_controller_definitions
526  * @{
527  */
528 #define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)
529 #define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)
530 
531 #define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
532  ((CTRL) == DMA_FlowCtrl_Peripheral))
533 /**
534  * @}
535  */
536 
537 
538 /** @defgroup DMA_memory_targets_definitions
539  * @{
540  */
541 #define DMA_Memory_0 ((uint32_t)0x00000000)
542 #define DMA_Memory_1 ((uint32_t)0x00080000)
543 
544 #define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
545 /**
546  * @}
547  */
548 
549 /**
550  * @}
551  */
552 
553 /* Exported macro ------------------------------------------------------------*/
554 /* Exported functions --------------------------------------------------------*/
555 
556 /* Function used to set the DMA configuration to the default reset state *****/
557 void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
558 
559 /* Initialization and Configuration functions *********************************/
560 void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
561 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
562 void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
563 
564 /* Optional Configuration functions *******************************************/
565 void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
566 void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
567 
568 /* Data Counter functions *****************************************************/
569 void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
570 uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
571 
572 /* Double Buffer mode functions ***********************************************/
573 void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
574  uint32_t DMA_CurrentMemory);
575 void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
576 void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
577  uint32_t DMA_MemoryTarget);
578 uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
579 
580 /* Interrupts and flags management functions **********************************/
581 FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
582 uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
583 FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
584 void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
585 void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
586 ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
587 void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
588 
589 #ifdef __cplusplus
590 }
591 #endif
592 
593 #endif /*__STM32F4xx_DMA_H */
594 
595 /**
596  * @}
597  */
598 
599 /**
600  * @}
601  */
602 
603 
604 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
DMA_InitTypeDef::DMA_MemoryInc
uint32_t DMA_MemoryInc
Definition: stm32f4xx_dma.h:70
DMA_InitTypeDef::DMA_Channel
uint32_t DMA_Channel
Definition: stm32f4xx_dma.h:50
DMA_InitTypeDef
DMA Init structure definition.
Definition: stm32f4xx_dma.h:48
DMA_InitTypeDef::DMA_MemoryBurst
uint32_t DMA_MemoryBurst
Definition: stm32f4xx_dma.h:95
DMA_InitTypeDef::DMA_MemoryDataSize
uint32_t DMA_MemoryDataSize
Definition: stm32f4xx_dma.h:76
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f4xx.h:460
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
DMA_InitTypeDef::DMA_DIR
uint32_t DMA_DIR
Definition: stm32f4xx_dma.h:59
DMA_InitTypeDef::DMA_PeripheralInc
uint32_t DMA_PeripheralInc
Definition: stm32f4xx_dma.h:67
DMA_InitTypeDef::DMA_PeripheralDataSize
uint32_t DMA_PeripheralDataSize
Definition: stm32f4xx_dma.h:73
DMA_InitTypeDef::DMA_PeripheralBurst
uint32_t DMA_PeripheralBurst
Definition: stm32f4xx_dma.h:100
DMA_InitTypeDef::DMA_PeripheralBaseAddr
uint32_t DMA_PeripheralBaseAddr
Definition: stm32f4xx_dma.h:53
DMA_InitTypeDef::DMA_Memory0BaseAddr
uint32_t DMA_Memory0BaseAddr
Definition: stm32f4xx_dma.h:55
DMA_InitTypeDef::DMA_FIFOThreshold
uint32_t DMA_FIFOThreshold
Definition: stm32f4xx_dma.h:92
DMA_InitTypeDef::DMA_FIFOMode
uint32_t DMA_FIFOMode
Definition: stm32f4xx_dma.h:87
DMA_InitTypeDef::DMA_Mode
uint32_t DMA_Mode
Definition: stm32f4xx_dma.h:79
DMA_InitTypeDef::DMA_BufferSize
uint32_t DMA_BufferSize
Definition: stm32f4xx_dma.h:63
DMA_InitTypeDef::DMA_Priority
uint32_t DMA_Priority
Definition: stm32f4xx_dma.h:84
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