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stm32f4xx_i2c.h
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1 /**
2  ******************************************************************************
3  * @file stm32f4xx_i2c.h
4  * @author MCD Application Team
5  * @version V1.0.0
6  * @date 30-September-2011
7  * @brief This file contains all the functions prototypes for the I2C firmware
8  * library.
9  ******************************************************************************
10  * @attention
11  *
12  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18  *
19  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
20  ******************************************************************************
21  */
22 
23 /* Define to prevent recursive inclusion -------------------------------------*/
24 #ifndef __STM32F4xx_I2C_H
25 #define __STM32F4xx_I2C_H
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 /* Includes ------------------------------------------------------------------*/
32 #include "stm32/stm32f4xx.h"
33 
34 /** @addtogroup STM32F4xx_StdPeriph_Driver
35  * @{
36  */
37 
38 /** @addtogroup I2C
39  * @{
40  */
41 
42 /* Exported types ------------------------------------------------------------*/
43 
44 /**
45  * @brief I2C Init structure definition
46  */
47 
48 typedef struct
49 {
50  uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
51  This parameter must be set to a value lower than 400kHz */
52 
53  uint16_t I2C_Mode; /*!< Specifies the I2C mode.
54  This parameter can be a value of @ref I2C_mode */
55 
56  uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
57  This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
58 
59  uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
60  This parameter can be a 7-bit or 10-bit address. */
61 
62  uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
63  This parameter can be a value of @ref I2C_acknowledgement */
64 
65  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
66  This parameter can be a value of @ref I2C_acknowledged_address */
67 }I2C_InitTypeDef;
68 
69 /* Exported constants --------------------------------------------------------*/
70 
71 
72 /** @defgroup I2C_Exported_Constants
73  * @{
74  */
75 
76 #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
77  ((PERIPH) == I2C2) || \
78  ((PERIPH) == I2C3))
79 /** @defgroup I2C_mode
80  * @{
81  */
82 
83 #define I2C_Mode_I2C ((uint16_t)0x0000)
84 #define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
85 #define I2C_Mode_SMBusHost ((uint16_t)0x000A)
86 #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
87  ((MODE) == I2C_Mode_SMBusDevice) || \
88  ((MODE) == I2C_Mode_SMBusHost))
89 /**
90  * @}
91  */
92 
93 /** @defgroup I2C_duty_cycle_in_fast_mode
94  * @{
95  */
96 
97 #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
98 #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
99 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
100  ((CYCLE) == I2C_DutyCycle_2))
101 /**
102  * @}
103  */
104 
105 /** @defgroup I2C_acknowledgement
106  * @{
107  */
108 
109 #define I2C_Ack_Enable ((uint16_t)0x0400)
110 #define I2C_Ack_Disable ((uint16_t)0x0000)
111 #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
112  ((STATE) == I2C_Ack_Disable))
113 /**
114  * @}
115  */
116 
117 /** @defgroup I2C_transfer_direction
118  * @{
119  */
120 
121 #define I2C_Direction_Transmitter ((uint8_t)0x00)
122 #define I2C_Direction_Receiver ((uint8_t)0x01)
123 #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
124  ((DIRECTION) == I2C_Direction_Receiver))
125 /**
126  * @}
127  */
128 
129 /** @defgroup I2C_acknowledged_address
130  * @{
131  */
132 
133 #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
134 #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
135 #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
136  ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
137 /**
138  * @}
139  */
140 
141 /** @defgroup I2C_registers
142  * @{
143  */
144 
145 #define I2C_Register_CR1 ((uint8_t)0x00)
146 #define I2C_Register_CR2 ((uint8_t)0x04)
147 #define I2C_Register_OAR1 ((uint8_t)0x08)
148 #define I2C_Register_OAR2 ((uint8_t)0x0C)
149 #define I2C_Register_DR ((uint8_t)0x10)
150 #define I2C_Register_SR1 ((uint8_t)0x14)
151 #define I2C_Register_SR2 ((uint8_t)0x18)
152 #define I2C_Register_CCR ((uint8_t)0x1C)
153 #define I2C_Register_TRISE ((uint8_t)0x20)
154 #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
155  ((REGISTER) == I2C_Register_CR2) || \
156  ((REGISTER) == I2C_Register_OAR1) || \
157  ((REGISTER) == I2C_Register_OAR2) || \
158  ((REGISTER) == I2C_Register_DR) || \
159  ((REGISTER) == I2C_Register_SR1) || \
160  ((REGISTER) == I2C_Register_SR2) || \
161  ((REGISTER) == I2C_Register_CCR) || \
162  ((REGISTER) == I2C_Register_TRISE))
163 /**
164  * @}
165  */
166 
167 /** @defgroup I2C_NACK_position
168  * @{
169  */
170 
171 #define I2C_NACKPosition_Next ((uint16_t)0x0800)
172 #define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
173 #define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
174  ((POSITION) == I2C_NACKPosition_Current))
175 /**
176  * @}
177  */
178 
179 /** @defgroup I2C_SMBus_alert_pin_level
180  * @{
181  */
182 
183 #define I2C_SMBusAlert_Low ((uint16_t)0x2000)
184 #define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
185 #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
186  ((ALERT) == I2C_SMBusAlert_High))
187 /**
188  * @}
189  */
190 
191 /** @defgroup I2C_PEC_position
192  * @{
193  */
194 
195 #define I2C_PECPosition_Next ((uint16_t)0x0800)
196 #define I2C_PECPosition_Current ((uint16_t)0xF7FF)
197 #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
198  ((POSITION) == I2C_PECPosition_Current))
199 /**
200  * @}
201  */
202 
203 /** @defgroup I2C_interrupts_definition
204  * @{
205  */
206 
207 #define I2C_IT_BUF ((uint16_t)0x0400)
208 #define I2C_IT_EVT ((uint16_t)0x0200)
209 #define I2C_IT_ERR ((uint16_t)0x0100)
210 #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
211 /**
212  * @}
213  */
214 
215 /** @defgroup I2C_interrupts_definition
216  * @{
217  */
218 
219 #define I2C_IT_SMBALERT ((uint32_t)0x01008000)
220 #define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
221 #define I2C_IT_PECERR ((uint32_t)0x01001000)
222 #define I2C_IT_OVR ((uint32_t)0x01000800)
223 #define I2C_IT_AF ((uint32_t)0x01000400)
224 #define I2C_IT_ARLO ((uint32_t)0x01000200)
225 #define I2C_IT_BERR ((uint32_t)0x01000100)
226 #define I2C_IT_TXE ((uint32_t)0x06000080)
227 #define I2C_IT_RXNE ((uint32_t)0x06000040)
228 #define I2C_IT_STOPF ((uint32_t)0x02000010)
229 #define I2C_IT_ADD10 ((uint32_t)0x02000008)
230 #define I2C_IT_BTF ((uint32_t)0x02000004)
231 #define I2C_IT_ADDR ((uint32_t)0x02000002)
232 #define I2C_IT_SB ((uint32_t)0x02000001)
233 
234 #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
235 
236 #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
237  ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
238  ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
239  ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
240  ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
241  ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
242  ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
243 /**
244  * @}
245  */
246 
247 /** @defgroup I2C_flags_definition
248  * @{
249  */
250 
251 /**
252  * @brief SR2 register flags
253  */
254 
255 #define I2C_FLAG_DUALF ((uint32_t)0x00800000)
256 #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
257 #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
258 #define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
259 #define I2C_FLAG_TRA ((uint32_t)0x00040000)
260 #define I2C_FLAG_BUSY ((uint32_t)0x00020000)
261 #define I2C_FLAG_MSL ((uint32_t)0x00010000)
262 
263 /**
264  * @brief SR1 register flags
265  */
266 
267 #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
268 #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
269 #define I2C_FLAG_PECERR ((uint32_t)0x10001000)
270 #define I2C_FLAG_OVR ((uint32_t)0x10000800)
271 #define I2C_FLAG_AF ((uint32_t)0x10000400)
272 #define I2C_FLAG_ARLO ((uint32_t)0x10000200)
273 #define I2C_FLAG_BERR ((uint32_t)0x10000100)
274 #define I2C_FLAG_TXE ((uint32_t)0x10000080)
275 #define I2C_FLAG_RXNE ((uint32_t)0x10000040)
276 #define I2C_FLAG_STOPF ((uint32_t)0x10000010)
277 #define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
278 #define I2C_FLAG_BTF ((uint32_t)0x10000004)
279 #define I2C_FLAG_ADDR ((uint32_t)0x10000002)
280 #define I2C_FLAG_SB ((uint32_t)0x10000001)
281 
282 #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
283 
284 #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
285  ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
286  ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
287  ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
288  ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
289  ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
290  ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
291  ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
292  ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
293  ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
294  ((FLAG) == I2C_FLAG_SB))
295 /**
296  * @}
297  */
298 
299 /** @defgroup I2C_Events
300  * @{
301  */
302 
303 /**
304  ===============================================================================
305  I2C Master Events (Events grouped in order of communication)
306  ===============================================================================
307  */
308 
309 /**
310  * @brief Communication start
311  *
312  * After sending the START condition (I2C_GenerateSTART() function) the master
313  * has to wait for this event. It means that the Start condition has been correctly
314  * released on the I2C bus (the bus is free, no other devices is communicating).
315  *
316  */
317 /* --EV5 */
318 #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
319 
320 /**
321  * @brief Address Acknowledge
322  *
323  * After checking on EV5 (start condition correctly released on the bus), the
324  * master sends the address of the slave(s) with which it will communicate
325  * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
326  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
327  * his address. If an acknowledge is sent on the bus, one of the following events will
328  * be set:
329  *
330  * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
331  * event is set.
332  *
333  * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
334  * is set
335  *
336  * 3) In case of 10-Bit addressing mode, the master (just after generating the START
337  * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
338  * function). Then master should wait on EV9. It means that the 10-bit addressing
339  * header has been correctly sent on the bus. Then master should send the second part of
340  * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
341  * should wait for event EV6.
342  *
343  */
344 
345 /* --EV6 */
346 #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
347 #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
348 /* --EV9 */
349 #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
350 
351 /**
352  * @brief Communication events
353  *
354  * If a communication is established (START condition generated and slave address
355  * acknowledged) then the master has to check on one of the following events for
356  * communication procedures:
357  *
358  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
359  * the data received from the slave (I2C_ReceiveData() function).
360  *
361  * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
362  * function) then to wait on event EV8 or EV8_2.
363  * These two events are similar:
364  * - EV8 means that the data has been written in the data register and is
365  * being shifted out.
366  * - EV8_2 means that the data has been physically shifted out and output
367  * on the bus.
368  * In most cases, using EV8 is sufficient for the application.
369  * Using EV8_2 leads to a slower communication but ensure more reliable test.
370  * EV8_2 is also more suitable than EV8 for testing on the last data transmission
371  * (before Stop condition generation).
372  *
373  * @note In case the user software does not guarantee that this event EV7 is
374  * managed before the current byte end of transfer, then user may check on EV7
375  * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
376  * In this case the communication may be slower.
377  *
378  */
379 
380 /* Master RECEIVER mode -----------------------------*/
381 /* --EV7 */
382 #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
383 
384 /* Master TRANSMITTER mode --------------------------*/
385 /* --EV8 */
386 #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
387 /* --EV8_2 */
388 #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
389 
390 
391 /**
392  ===============================================================================
393  I2C Slave Events (Events grouped in order of communication)
394  ===============================================================================
395  */
396 
397 
398 /**
399  * @brief Communication start events
400  *
401  * Wait on one of these events at the start of the communication. It means that
402  * the I2C peripheral detected a Start condition on the bus (generated by master
403  * device) followed by the peripheral address. The peripheral generates an ACK
404  * condition on the bus (if the acknowledge feature is enabled through function
405  * I2C_AcknowledgeConfig()) and the events listed above are set :
406  *
407  * 1) In normal case (only one address managed by the slave), when the address
408  * sent by the master matches the own address of the peripheral (configured by
409  * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
410  * (where XXX could be TRANSMITTER or RECEIVER).
411  *
412  * 2) In case the address sent by the master matches the second address of the
413  * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
414  * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
415  * (where XXX could be TRANSMITTER or RECEIVER) are set.
416  *
417  * 3) In case the address sent by the master is General Call (address 0x00) and
418  * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
419  * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
420  *
421  */
422 
423 /* --EV1 (all the events below are variants of EV1) */
424 /* 1) Case of One Single Address managed by the slave */
425 #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
426 #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
427 
428 /* 2) Case of Dual address managed by the slave */
429 #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
430 #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
431 
432 /* 3) Case of General Call enabled for the slave */
433 #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
434 
435 /**
436  * @brief Communication events
437  *
438  * Wait on one of these events when EV1 has already been checked and:
439  *
440  * - Slave RECEIVER mode:
441  * - EV2: When the application is expecting a data byte to be received.
442  * - EV4: When the application is expecting the end of the communication: master
443  * sends a stop condition and data transmission is stopped.
444  *
445  * - Slave Transmitter mode:
446  * - EV3: When a byte has been transmitted by the slave and the application is expecting
447  * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
448  * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
449  * used when the user software doesn't guarantee the EV3 is managed before the
450  * current byte end of transfer.
451  * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
452  * shall end (before sending the STOP condition). In this case slave has to stop sending
453  * data bytes and expect a Stop condition on the bus.
454  *
455  * @note In case the user software does not guarantee that the event EV2 is
456  * managed before the current byte end of transfer, then user may check on EV2
457  * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
458  * In this case the communication may be slower.
459  *
460  */
461 
462 /* Slave RECEIVER mode --------------------------*/
463 /* --EV2 */
464 #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
465 /* --EV4 */
466 #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
467 
468 /* Slave TRANSMITTER mode -----------------------*/
469 /* --EV3 */
470 #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
471 #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
472 /* --EV3_2 */
473 #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
474 
475 /*
476  ===============================================================================
477  End of Events Description
478  ===============================================================================
479  */
480 
481 #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
482  ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
483  ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
484  ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
485  ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
486  ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
487  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
488  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
489  ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
490  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
491  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
492  ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
493  ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
494  ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
495  ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
496  ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
497  ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
498  ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
499  ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
500  ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
501 /**
502  * @}
503  */
504 
505 /** @defgroup I2C_own_address1
506  * @{
507  */
508 
509 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
510 /**
511  * @}
512  */
513 
514 /** @defgroup I2C_clock_speed
515  * @{
516  */
517 
518 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
519 /**
520  * @}
521  */
522 
523 /**
524  * @}
525  */
526 
527 /* Exported macro ------------------------------------------------------------*/
528 /* Exported functions --------------------------------------------------------*/
529 
530 /* Function used to set the I2C configuration to the default reset state *****/
531 void I2C_DeInit(I2C_TypeDef* I2Cx);
532 
533 /* Initialization and Configuration functions *********************************/
534 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
535 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
536 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
537 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
538 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
539 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
540 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
541 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
542 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
543 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
544 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
545 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
546 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
547 void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
548 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
549 void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
550 
551 /* Data transfers functions ***************************************************/
552 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
553 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
554 
555 /* PEC management functions ***************************************************/
556 void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
557 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
558 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
559 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
560 
561 /* DMA transfers management functions *****************************************/
562 void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
563 void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
564 
565 /* Interrupts, events and flags management functions **************************/
566 uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
567 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
568 
569 /*
570  ===============================================================================
571  I2C State Monitoring Functions
572  ===============================================================================
573  This I2C driver provides three different ways for I2C state monitoring
574  depending on the application requirements and constraints:
575 
576 
577  1. Basic state monitoring (Using I2C_CheckEvent() function)
578  -----------------------------------------------------------
579  It compares the status registers (SR1 and SR2) content to a given event
580  (can be the combination of one or more flags).
581  It returns SUCCESS if the current status includes the given flags
582  and returns ERROR if one or more flags are missing in the current status.
583 
584  - When to use
585  - This function is suitable for most applications as well as for startup
586  activity since the events are fully described in the product reference
587  manual (RM0090).
588  - It is also suitable for users who need to define their own events.
589 
590  - Limitations
591  - If an error occurs (ie. error flags are set besides to the monitored
592  flags), the I2C_CheckEvent() function may return SUCCESS despite
593  the communication hold or corrupted real state.
594  In this case, it is advised to use error interrupts to monitor
595  the error events and handle them in the interrupt IRQ handler.
596 
597  Note
598  For error management, it is advised to use the following functions:
599  - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
600  - I2Cx_ER_IRQ_Handler() which is called when the error interrupt occurs.
601  Where x is the peripheral instance (I2C1, I2C2 ...)
602  - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
603  I2Cx_ER_IRQ_Handler() function in order to determine which error occurred.
604  - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
605  and/or I2C_GenerateStop() in order to clear the error flag and source
606  and return to correct communication status.
607 
608 
609  2. Advanced state monitoring (Using the function I2C_GetLastEvent())
610  --------------------------------------------------------------------
611  Using the function I2C_GetLastEvent() which returns the image of both status
612  registers in a single word (uint32_t) (Status Register 2 value is shifted left
613  by 16 bits and concatenated to Status Register 1).
614 
615  - When to use
616  - This function is suitable for the same applications above but it
617  allows to overcome the mentioned limitation of I2C_GetFlagStatus()
618  function.
619  - The returned value could be compared to events already defined in
620  this file or to custom values defined by user.
621  This function is suitable when multiple flags are monitored at the
622  same time.
623  - At the opposite of I2C_CheckEvent() function, this function allows
624  user to choose when an event is accepted (when all events flags are
625  set and no other flags are set or just when the needed flags are set
626  like I2C_CheckEvent() function.
627 
628  - Limitations
629  - User may need to define his own events.
630  - Same remark concerning the error management is applicable for this
631  function if user decides to check only regular communication flags
632  (and ignores error flags).
633 
634 
635  3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
636  -----------------------------------------------------------------------
637 
638  Using the function I2C_GetFlagStatus() which simply returns the status of
639  one single flag (ie. I2C_FLAG_RXNE ...).
640 
641  - When to use
642  - This function could be used for specific applications or in debug
643  phase.
644  - It is suitable when only one flag checking is needed (most I2C
645  events are monitored through multiple flags).
646  - Limitations:
647  - When calling this function, the Status register is accessed.
648  Some flags are cleared when the status register is accessed.
649  So checking the status of one Flag, may clear other ones.
650  - Function may need to be called twice or more in order to monitor
651  one single event.
652  */
653 
654 /*
655  ===============================================================================
656  1. Basic state monitoring
657  ===============================================================================
658  */
659 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
660 /*
661  ===============================================================================
662  2. Advanced state monitoring
663  ===============================================================================
664  */
665 uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
666 /*
667  ===============================================================================
668  3. Flag-based state monitoring
669  ===============================================================================
670  */
671 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
672 
673 
674 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
675 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
676 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
677 
678 #ifdef __cplusplus
679 }
680 #endif
681 
682 #endif /*__STM32F4xx_I2C_H */
683 
684 /**
685  * @}
686  */
687 
688 /**
689  * @}
690  */
691 
692 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
I2C_InitTypeDef::I2C_Ack
uint16_t I2C_Ack
Definition: stm32f4xx_i2c.h:62
I2C_InitTypeDef::I2C_AcknowledgedAddress
uint16_t I2C_AcknowledgedAddress
Definition: stm32f4xx_i2c.h:65
I2C_InitTypeDef::I2C_OwnAddress1
uint16_t I2C_OwnAddress1
Definition: stm32f4xx_i2c.h:59
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
I2C_InitTypeDef::I2C_ClockSpeed
uint32_t I2C_ClockSpeed
Definition: stm32f4xx_i2c.h:50
I2C_InitTypeDef
I2C Init structure definition.
Definition: stm32f4xx_i2c.h:48
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f4xx.h:674
I2C_InitTypeDef::I2C_DutyCycle
uint16_t I2C_DutyCycle
Definition: stm32f4xx_i2c.h:56
I2C_InitTypeDef::I2C_Mode
uint16_t I2C_Mode
Definition: stm32f4xx_i2c.h:53
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