audio_stm32.c

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/************************************************************************//**
 * \file heivs/audio_stm32.c
 * \brief ARMEBS4 audio for stm32
 * \author marc dot pignat at hevs dot ch & Pascal Sartoretti (sap at hevs dot ch)
 ***************************************************************************/

#include "heivs/audio_stm32.h"
#include "heivs/bsp.h"
#include "stm32/stm32f4xx_rcc.h"
#include "stm32/stm32f4xx_spi.h"
#include "stm32/stm32f4xx_dma.h"
#include "stm32/stm32f4xx_misc.h"
#include "heivs/stm32_gpio.h"

#include "heivs/config.h"
#if USE_FREERTOS
#include "freertos/FreeRTOS.h"
#endif

#define DMA_Stream_RX DMA1_Stream3
#define DMA_Stream_TX DMA1_Stream4
#define DMA_Stream_RX_IRQn DMA1_Stream3_IRQn
#define DMA_Stream_TX_IRQn DMA1_Stream4_IRQn

/**
 * \brief Predefined audio setup
 */
struct audio_setup_t
{
    uint32_t fs;
    uint32_t fs_i2s;
    uint32_t pll_sn;
    uint32_t pll_sr;
    uint32_t sample_size;
    uint32_t byte_per_sample;
};

/**
 * \brief Table of all currently supported setups
 */
static const struct audio_setup_t audio_setups[] =
{
    {
        .fs = 48000,
        .fs_i2s = I2S_AudioFreq_48k,
        .pll_sn = 258,
        .pll_sr = 3,
    },
    {
        .fs = 44100,
        .fs_i2s = I2S_AudioFreq_44k,
        .pll_sn = 271,
        .pll_sr = 2,
    },
    {
        .fs = 96000,
        .fs_i2s = I2S_AudioFreq_96k,
        .pll_sn = 344,
        .pll_sr = 2,
    },
    {
        .fs = 32000,
        .fs_i2s = I2S_AudioFreq_32k,
        .pll_sn = 213,
        .pll_sr = 2,
    },
    {
        .fs = 16000,
        .fs_i2s = I2S_AudioFreq_16k,
        .pll_sn = 213,
        .pll_sr = 2,
    },
    {
        .fs = 8000,
        .fs_i2s = I2S_AudioFreq_8k,
        .pll_sn = 256,
        .pll_sr = 5,
    },
};

/**
 * \brief DMA transfer
 */
static struct dma_xfer_t dma_play_xfer;
static struct dma_xfer_t dma_record_xfer;

/**
 * The current audio setup
 */
static struct audio_setup_t setup;

/**
 * \brief Description of a DMA transfer
 */
struct dma_xfer_t
{
    uint32_t tx_zeroes;

    void (*done)(const void *); ///< Handler called at the end of Audio_DMA_Play
    void *data[2];              ///< Buffers
    uint32_t length;
    volatile void *next_buffer;
    volatile uint32_t buffer_needed;
};

/**
 * \brief Find the correct setup
 *
 * \param fs, the sampling frequency
 *
 * \return a pointer to the configuration or NULL if the frequency is not supported
 */
static status_e audio_setup_selection(struct audio_setup_t *setup, uint32_t fs, uint32_t sample_size)
{
    size_t i;
    int32_t found = -1;

    for (i = 0 ; i < ARRAY_SIZE(audio_setups); i++)
    {
        if (audio_setups[i].fs == fs)
        {
            found = i;
            break;
        }
    }

    if (found == -1)
    {
        return ERROR_BAD_PARAM;
    }

    memcpy(setup, &audio_setups[i], sizeof(*setup));

    switch (sample_size)
    {
        case 16:
            setup->sample_size = I2S_DataFormat_16bextended;
            setup->byte_per_sample = 2;
        break;
        case 24:
            setup->sample_size = I2S_DataFormat_24b;
            setup->byte_per_sample = 3;
        break;
        case 32:
            setup->sample_size = I2S_DataFormat_32b;
            setup->byte_per_sample = 4;
        break;

        default:
            return ERROR_BAD_PARAM;
    }

    return NO_ERROR;
}



static const uint16_t nop[4];
static void tx_zeroes(void)
{
    DMA_ITConfig(DMA_Stream_TX, DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME, DISABLE);
    DMA_ITConfig(DMA_Stream_TX, DMA_IT_FE, DISABLE);

    DMA_Stream_TX->NDTR = ARRAY_SIZE(nop);
    DMA_Stream_TX->M0AR = (uint32_t)&nop[0];
    DMA_Stream_TX->M1AR = (uint32_t)&nop[0];
    DMA_DoubleBufferModeCmd(DMA_Stream_TX, ENABLE);

    /* Enable the I2S DMA Stream */
    DMA_Cmd(DMA_Stream_TX, ENABLE);
}

static void i2s_dma_tx_irq_handler(void)
{
    /* FIFO Error interrupt */
    if (DMA_GetFlagStatus(DMA_Stream_TX, DMA_FLAG_FEIF4) != RESET)
    {
        /* Clear the Interrupt flag */
        DMA_ClearFlag(DMA_Stream_TX, DMA_FLAG_FEIF4);
    }

    /* Transfer error interrupt */
    if (DMA_GetFlagStatus(DMA_Stream_TX, DMA_FLAG_DMEIF4) || DMA_GetFlagStatus(DMA_Stream_TX, DMA_FLAG_TEIF4))
    {
        DMA_ITConfig(DMA_Stream_TX, DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME, DISABLE);
        DMA_ITConfig(DMA_Stream_TX, DMA_IT_FE, DISABLE);

        /* Clear the Interrupt flag */
        DMA_ClearFlag(DMA_Stream_TX, DMA_FLAG_DMEIF4);
        DMA_ClearFlag(DMA_Stream_TX, DMA_FLAG_TEIF4);
    }

    if (DMA_GetFlagStatus(DMA_Stream_TX, DMA_FLAG_HTIF4) != RESET)
    {
        switch (DMA_GetCurrentMemoryTarget(DMA_Stream_TX))
        {
            case 0:
                dma_play_xfer.next_buffer = dma_play_xfer.data[0];
            break;

            case 1:
                dma_play_xfer.next_buffer = dma_play_xfer.data[1];
            break;

            default:
                bsp_fatal(ERROR_BAD_SWITCH);
            break;
        }

        // Clear the flag
        DMA_ClearFlag(DMA_Stream_TX, DMA_FLAG_HTIF4);
    }

    // Xfer complete
    if (DMA_GetFlagStatus(DMA_Stream_TX, DMA_FLAG_TCIF4) != RESET)
    {
        dma_play_xfer.buffer_needed = 1;

        if (dma_play_xfer.done)
        {
            dma_play_xfer.done((void *)dma_play_xfer.next_buffer);
        }

        // Clear the flag
        DMA_ClearFlag(DMA_Stream_TX, DMA_FLAG_TCIF4);
    }
}

static void i2s_dma_rx_irq_handler(void)
{
    /* FIFO Error interrupt */
    if (DMA_GetFlagStatus(DMA_Stream_RX, DMA_FLAG_FEIF3) != RESET)
    {
        /* Clear the Interrupt flag */
        DMA_ClearFlag(DMA_Stream_RX, DMA_FLAG_FEIF3);
    }

    /* Transfer error interrupt */
    if (DMA_GetFlagStatus(DMA_Stream_RX, DMA_FLAG_DMEIF3) || DMA_GetFlagStatus(DMA_Stream_RX, DMA_FLAG_TEIF3))
    {
        DMA_ITConfig(DMA_Stream_RX, DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME, DISABLE);
        DMA_ITConfig(DMA_Stream_RX, DMA_IT_FE, DISABLE);

        /* Clear the Interrupt flag */
        DMA_ClearFlag(DMA_Stream_RX, DMA_FLAG_DMEIF3);
        DMA_ClearFlag(DMA_Stream_RX, DMA_FLAG_TEIF3);
    }
    if (DMA_GetFlagStatus(DMA_Stream_RX, DMA_FLAG_HTIF3) != RESET)
    {
        switch (DMA_GetCurrentMemoryTarget(DMA_Stream_RX))
        {
            case 0:
                dma_record_xfer.next_buffer = dma_record_xfer.data[0];
            break;

            case 1:
                dma_record_xfer.next_buffer = dma_record_xfer.data[1];
            break;

            default:
                bsp_fatal(ERROR_BAD_SWITCH);
            break;
        }

        DMA_ClearFlag(DMA_Stream_RX, DMA_FLAG_HTIF3);
    }

    // Xfer complete
    if (DMA_GetFlagStatus(DMA_Stream_RX, DMA_FLAG_TCIF3) != RESET)
    {
        dma_record_xfer.done((void*)dma_record_xfer.next_buffer);

        // Clear the flag
        DMA_ClearFlag(DMA_Stream_RX, DMA_FLAG_TCIF3);
    }
}

status_e AudioSTM32_Init(uint32_t fs, uint32_t sample_size)
{
    I2S_InitTypeDef i2sStruct;
    status_e status;
    status = audio_setup_selection(&setup, fs, sample_size);
    if (status != NO_ERROR)
    {
        return status;
    }

    // Setup pins
    const struct gpio_t pins[] =
    {
        GPIO_I2S2_MCK_PC6,
        GPIO_I2S2_WS_PB12,
        GPIO_I2S2_CK_PB13,
        GPIO_I2S2ext_SD_PI2,
        GPIO_I2S2_SD_PI3,
    };
    gpio_setup_list(pins, ARRAY_SIZE(pins));

    //---------------------------------------------------------------------------
    // ensure de init I2S from previous states
    SPI_I2S_DeInit(SPI2);
    //---------------------------------------------------------------------------
    // setup clock for I2S (on SPI 2)
    RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S);
    RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
    RCC_PLLI2SConfig(setup.pll_sn, setup.pll_sr);       // setup PLL freq
    RCC_PLLI2SCmd(ENABLE);
    while(RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY)!= SET)
    {}
    //---------------------------------------------------------------------------
    // setup I2S working mode
    i2sStruct.I2S_Mode = I2S_Mode_MasterTx;
    i2sStruct.I2S_Standard = I2S_Standard_Phillips;     // I2S standard
    i2sStruct.I2S_DataFormat = setup.sample_size;
    i2sStruct.I2S_MCLKOutput = I2S_MCLKOutput_Enable;   // enable MCK
    i2sStruct.I2S_CPOL = I2S_CPOL_Low;
    i2sStruct.I2S_AudioFreq = setup.fs_i2s;             // set sample freq

    I2S_Init(SPI2, &i2sStruct);
    I2S_FullDuplexConfig(I2S2ext, &i2sStruct);          // use recording too

    I2S_Cmd(SPI2, ENABLE);                              // enable output
    I2S_Cmd(I2S2ext, ENABLE);                           // enable input

    // DMA output
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
    DMA_InitTypeDef DMA_InitStructure;
    DMA_StructInit(&DMA_InitStructure);

    DMA_Cmd(DMA_Stream_TX, DISABLE);
    DMA_DeInit(DMA_Stream_TX);
    DMA_InitStructure.DMA_Channel = DMA_Channel_0;
    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI2->DR;
    DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0;
    DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
    DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE;
    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
    DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
    DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
    DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
    DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
    DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
    DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
    DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
    DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
    DMA_Init(DMA_Stream_TX, &DMA_InitStructure);

    /* I2S DMA IRQ Channel configuration */
    NVIC_InitTypeDef NVIC_InitStructure;
    NVIC_InitStructure.NVIC_IRQChannel = DMA_Stream_TX_IRQn;
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
    NVIC_InitStructure.NVIC_Handler = i2s_dma_tx_irq_handler;
    NVIC_Init(&NVIC_InitStructure);

    DMA_ITConfig(DMA_Stream_TX, DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME, ENABLE);
    DMA_ITConfig(DMA_Stream_TX, DMA_IT_FE, ENABLE);

    SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);

    // DMA input
    DMA_StructInit(&DMA_InitStructure);

    DMA_Cmd(DMA_Stream_RX, DISABLE);
    DMA_DeInit(DMA_Stream_RX);
    DMA_InitStructure.DMA_Channel = DMA_Channel_3;
    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&I2S2ext->DR;
    DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0;
    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
    DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE;
    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
    DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
    DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
    DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
    DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
    DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
    DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
    DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
    DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
    DMA_Init(DMA_Stream_RX, &DMA_InitStructure);

    DMA_ITConfig(DMA_Stream_RX, DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME, ENABLE);
    DMA_ITConfig(DMA_Stream_RX, DMA_IT_FE, ENABLE);

    /* I2S DMA IRQ Channel configuration */
    NVIC_InitStructure.NVIC_IRQChannel = DMA_Stream_RX_IRQn;
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
    NVIC_InitStructure.NVIC_Handler = i2s_dma_rx_irq_handler;
    NVIC_Init(&NVIC_InitStructure);

    SPI_I2S_DMACmd(I2S2ext, SPI_I2S_DMAReq_Rx, ENABLE);

    return NO_ERROR;
}

status_e AudioSTM32_Stream_Play_Init(uint32_t length, void *buffer0, void *buffer1, void (*done)(const void *))
{
    if (length & 1)
    {
        return ERROR_BAD_PARAM;
    }

    length /=2;

    if (length > DMA_MAX_XFER_COUNT)
    {
        return ERROR_BAD_PARAM;
    }

    if (buffer0 == buffer1)
    {
        return ERROR_BAD_PARAM;
    }

    if (((uint32_t)buffer0 & 1) || ((uint32_t)buffer1 & 1))
    {
        return ERROR_BAD_ALIGN;
    }

    if (DMA_GetCmdStatus(DMA_Stream_TX))
    {
        return ERROR_BAD_STATE;
    }

    memset(&dma_play_xfer, 0x0, sizeof(dma_play_xfer));
    dma_play_xfer.data[0] = buffer0;
    dma_play_xfer.data[1] = buffer1;
    dma_play_xfer.length = length;

    DMA_Stream_TX->NDTR = length;
    DMA_Stream_TX->M0AR = (uint32_t)dma_play_xfer.data[0];
    DMA_Stream_TX->M1AR = (uint32_t)dma_play_xfer.data[1];
    dma_play_xfer.done = done;
    DMA_DoubleBufferModeCmd(DMA_Stream_TX, ENABLE);

    AudioSTM32_Stream_Play_Pause();

    DMA_ITConfig(DMA_Stream_TX, DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME, ENABLE);
    DMA_ITConfig(DMA_Stream_TX, DMA_IT_FE, ENABLE);

    /* Enable the I2S DMA Stream */
    DMA_Cmd(DMA_Stream_TX, ENABLE);

    return NO_ERROR;
}

status_e AudioSTM32_Stream_Play_Pause(void)
{
    memset(dma_play_xfer.data[0], 0x0, dma_play_xfer.length * 2);
    memset(dma_play_xfer.data[1], 0x0, dma_play_xfer.length * 2);

    return NO_ERROR;
}

status_e AudioSTM32_Stream_Play_Stop(void)
{
    DMA_Cmd(DMA_Stream_TX, DISABLE);

    return NO_ERROR;
}

status_e AudioSTM32_Stream_Play_Status(void)
{
    if (dma_play_xfer.buffer_needed == 0)
    {
        return ERROR_AGAIN;
    }

    return NO_ERROR;
}

status_e AudioSTM32_Stream_Play(const void *data)
{
    status_e status;

    while (1)
    {
        status = AudioSTM32_Stream_Play_Status();
        if (status == NO_ERROR)
        {
            // Ready for next buffer
            break;
        }

        if (status == ERROR_AGAIN)
        {
            // Should wait
            #if USE_FREERTOS
            // FIXME : use something like an event
            vTaskDelay(1);
            #else
            // Stream will be changed in interrupt, so wait for it
            __WFI();
            #endif
        }
        else
        {
            // Another error
            return status;
        }
    }

    // Copy the buffer
    memcpy((void *)dma_play_xfer.next_buffer, data, dma_play_xfer.length * 2);
    dma_play_xfer.buffer_needed = 0;

    return NO_ERROR;
}

static void send_when_ready(uint16_t data)
{
    while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET){}
    SPI_I2S_SendData(SPI2, data);
}

status_e AudioSTM32_Play(const int16_t *src, uint32_t length)
{
    uint32_t i;

    length /=2;
    for (i = 0 ; i < length; i++)
    {
        send_when_ready(src[i]);
    }

    return NO_ERROR;
}

status_e AudioSTM32_Record(int16_t *dst, uint32_t length)
{
    length /= 2;
    uint32_t counter=0;

    // send a dummy byte more -> so it works !!!
    while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET){}
    SPI_I2S_SendData(SPI2, 0);

    do
    {
        while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET){}
        SPI_I2S_SendData(SPI2,0);
        while (SPI_I2S_GetFlagStatus(I2S2ext, SPI_FLAG_RXNE) == RESET){}
        dst[counter] = SPI_I2S_ReceiveData(I2S2ext);
        counter++;
    }while(counter < length);
    return NO_ERROR;
}

status_e AudioSTM32_Stream_Record_Init(uint32_t length, void *buffer0, void *buffer1, void(*done)(const void *))
{
    if (!length || !done)
    {
        return ERROR_BAD_PARAM;
    }

    if (length & 1)
    {
        return ERROR_BAD_PARAM;
    }

    length /=2;

    if (length > DMA_MAX_XFER_COUNT)
    {
        return ERROR_BAD_PARAM;
    }

    if (!buffer0 || !buffer1)
    {
        return ERROR_BAD_PARAM;
    }

    if (buffer0 == buffer1)
    {
        return ERROR_BAD_PARAM;
    }

    if (((uint32_t)buffer0 & 1) || ((uint32_t)buffer1 & 1))
    {
        return ERROR_BAD_ALIGN;
    }


    memset(&dma_record_xfer, 0x0, sizeof(dma_record_xfer));
    dma_record_xfer.done = done;
    dma_record_xfer.length = length;
    dma_record_xfer.data[0] = buffer0;
    dma_record_xfer.data[1] = buffer1;

    DMA_Stream_RX->NDTR = dma_record_xfer.length;
    DMA_Stream_RX->M0AR = (uint32_t)dma_record_xfer.data[0];
    DMA_Stream_RX->M1AR = (uint32_t)dma_record_xfer.data[1];
    DMA_DoubleBufferModeCmd(DMA_Stream_RX, ENABLE);

    DMA_ITConfig(DMA_Stream_RX, DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME, ENABLE);
    DMA_ITConfig(DMA_Stream_RX, DMA_IT_FE, ENABLE);

    /* Send zeros if DMA output is disable */
    if (!DMA_GetCmdStatus(DMA_Stream_TX))
    {
        dma_record_xfer.tx_zeroes = 1;
        tx_zeroes();
    }

    /* Enable the I2S DMA Stream */
    DMA_Cmd(DMA_Stream_RX, ENABLE);

    return NO_ERROR;
}

status_e AudioSTM32_Stream_Record_Stop(void)
{
    DMA_Cmd(DMA_Stream_RX, DISABLE);

    DMA_ITConfig(DMA_Stream_RX, DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME, DISABLE);
    DMA_ITConfig(DMA_Stream_RX, DMA_IT_FE, DISABLE);

    if (dma_record_xfer.tx_zeroes)
    {
        DMA_Cmd(DMA_Stream_TX, DISABLE);
    }

    return NO_ERROR;
}