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stm32f4xx_adc.h
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1 /**
2  ******************************************************************************
3  * @file stm32f4xx_adc.h
4  * @author MCD Application Team
5  * @version V1.0.0
6  * @date 30-September-2011
7  * @brief This file contains all the functions prototypes for the ADC firmware
8  * library.
9  ******************************************************************************
10  * @attention
11  *
12  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18  *
19  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
20  ******************************************************************************
21  */
22 
23 /* Define to prevent recursive inclusion -------------------------------------*/
24 #ifndef __STM32F4xx_ADC_H
25 #define __STM32F4xx_ADC_H
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 /* Includes ------------------------------------------------------------------*/
32 #include "stm32/stm32f4xx.h"
33 
34 /** @addtogroup STM32F4xx_StdPeriph_Driver
35  * @{
36  */
37 
38 /** @addtogroup ADC
39  * @{
40  */
41 
42 /* Exported types ------------------------------------------------------------*/
43 
44 /**
45  * @brief ADC Init structure definition
46  */
47 typedef struct
48 {
49  uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode.
50  This parameter can be a value of @ref ADC_resolution */
51  FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion
52  is performed in Scan (multichannels)
53  or Single (one channel) mode.
54  This parameter can be set to ENABLE or DISABLE */
55  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion
56  is performed in Continuous or Single mode.
57  This parameter can be set to ENABLE or DISABLE. */
58  uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and
59  enable the trigger of a regular group.
60  This parameter can be a value of
61  @ref ADC_external_trigger_edge_for_regular_channels_conversion */
62  uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger
63  the start of conversion of a regular group.
64  This parameter can be a value of
65  @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
66  uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment
67  is left or right. This parameter can be
68  a value of @ref ADC_data_align */
69  uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions
70  that will be done using the sequencer for
71  regular channel group.
72  This parameter must range from 1 to 16. */
73 }ADC_InitTypeDef;
74 
75 /**
76  * @brief ADC Common Init structure definition
77  */
78 typedef struct
79 {
80  uint32_t ADC_Mode; /*!< Configures the ADC to operate in
81  independent or multi mode.
82  This parameter can be a value of @ref ADC_Common_mode */
83  uint32_t ADC_Prescaler; /*!< Select the frequency of the clock
84  to the ADC. The clock is common for all the ADCs.
85  This parameter can be a value of @ref ADC_Prescaler */
86  uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access
87  mode for multi ADC mode.
88  This parameter can be a value of
89  @ref ADC_Direct_memory_access_mode_for_multi_mode */
90  uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
91  This parameter can be a value of
92  @ref ADC_delay_between_2_sampling_phases */
93 
94 }ADC_CommonInitTypeDef;
95 
96 
97 /* Exported constants --------------------------------------------------------*/
98 
99 /** @defgroup ADC_Exported_Constants
100  * @{
101  */
102 #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
103  ((PERIPH) == ADC2) || \
104  ((PERIPH) == ADC3))
105 
106 /** @defgroup ADC_Common_mode
107  * @{
108  */
109 #define ADC_Mode_Independent ((uint32_t)0x00000000)
110 #define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)
111 #define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)
112 #define ADC_DualMode_InjecSimult ((uint32_t)0x00000005)
113 #define ADC_DualMode_RegSimult ((uint32_t)0x00000006)
114 #define ADC_DualMode_Interl ((uint32_t)0x00000007)
115 #define ADC_DualMode_AlterTrig ((uint32_t)0x00000009)
116 #define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)
117 #define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)
118 #define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)
119 #define ADC_TripleMode_RegSimult ((uint32_t)0x00000016)
120 #define ADC_TripleMode_Interl ((uint32_t)0x00000017)
121 #define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)
122 #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
123  ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
124  ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
125  ((MODE) == ADC_DualMode_InjecSimult) || \
126  ((MODE) == ADC_DualMode_RegSimult) || \
127  ((MODE) == ADC_DualMode_Interl) || \
128  ((MODE) == ADC_DualMode_AlterTrig) || \
129  ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
130  ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
131  ((MODE) == ADC_TripleMode_InjecSimult) || \
132  ((MODE) == ADC_TripleMode_RegSimult) || \
133  ((MODE) == ADC_TripleMode_Interl) || \
134  ((MODE) == ADC_TripleMode_AlterTrig))
135 /**
136  * @}
137  */
138 
139 
140 /** @defgroup ADC_Prescaler
141  * @{
142  */
143 #define ADC_Prescaler_Div2 ((uint32_t)0x00000000)
144 #define ADC_Prescaler_Div4 ((uint32_t)0x00010000)
145 #define ADC_Prescaler_Div6 ((uint32_t)0x00020000)
146 #define ADC_Prescaler_Div8 ((uint32_t)0x00030000)
147 #define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
148  ((PRESCALER) == ADC_Prescaler_Div4) || \
149  ((PRESCALER) == ADC_Prescaler_Div6) || \
150  ((PRESCALER) == ADC_Prescaler_Div8))
151 /**
152  * @}
153  */
154 
155 
156 /** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
157  * @{
158  */
159 #define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */
160 #define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
161 #define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
162 #define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
163 #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
164  ((MODE) == ADC_DMAAccessMode_1) || \
165  ((MODE) == ADC_DMAAccessMode_2) || \
166  ((MODE) == ADC_DMAAccessMode_3))
167 
168 /**
169  * @}
170  */
171 
172 
173 /** @defgroup ADC_delay_between_2_sampling_phases
174  * @{
175  */
176 #define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)
177 #define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100)
178 #define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200)
179 #define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300)
180 #define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400)
181 #define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500)
182 #define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600)
183 #define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700)
184 #define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800)
185 #define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900)
186 #define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00)
187 #define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00)
188 #define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00)
189 #define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00)
190 #define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00)
191 #define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)
192 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
193  ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
194  ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
195  ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
196  ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
197  ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
198  ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
199  ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
200  ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
201  ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
202  ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
203  ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
204  ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
205  ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
206  ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
207  ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
208 
209 /**
210  * @}
211  */
212 
213 
214 /** @defgroup ADC_resolution
215  * @{
216  */
217 #define ADC_Resolution_12b ((uint32_t)0x00000000)
218 #define ADC_Resolution_10b ((uint32_t)0x01000000)
219 #define ADC_Resolution_8b ((uint32_t)0x02000000)
220 #define ADC_Resolution_6b ((uint32_t)0x03000000)
221 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
222  ((RESOLUTION) == ADC_Resolution_10b) || \
223  ((RESOLUTION) == ADC_Resolution_8b) || \
224  ((RESOLUTION) == ADC_Resolution_6b))
225 
226 /**
227  * @}
228  */
229 
230 
231 /** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
232  * @{
233  */
234 #define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
235 #define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
236 #define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
237 #define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
238 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
239  ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
240  ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
241  ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
242 /**
243  * @}
244  */
245 
246 
247 /** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion
248  * @{
249  */
250 #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
251 #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000)
252 #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000)
253 #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
254 #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000)
255 #define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000)
256 #define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
257 #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
258 #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000)
259 #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000)
260 #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000)
261 #define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000)
262 #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000)
263 #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000)
264 #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000)
265 #define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
266 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
267  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
268  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
269  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
270  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
271  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
272  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
273  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
274  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
275  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
276  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
277  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
278  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
279  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
280  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
281  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
282 /**
283  * @}
284  */
285 
286 
287 /** @defgroup ADC_data_align
288  * @{
289  */
290 #define ADC_DataAlign_Right ((uint32_t)0x00000000)
291 #define ADC_DataAlign_Left ((uint32_t)0x00000800)
292 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
293  ((ALIGN) == ADC_DataAlign_Left))
294 /**
295  * @}
296  */
297 
298 
299 /** @defgroup ADC_channels
300  * @{
301  */
302 #define ADC_Channel_0 ((uint8_t)0x00)
303 #define ADC_Channel_1 ((uint8_t)0x01)
304 #define ADC_Channel_2 ((uint8_t)0x02)
305 #define ADC_Channel_3 ((uint8_t)0x03)
306 #define ADC_Channel_4 ((uint8_t)0x04)
307 #define ADC_Channel_5 ((uint8_t)0x05)
308 #define ADC_Channel_6 ((uint8_t)0x06)
309 #define ADC_Channel_7 ((uint8_t)0x07)
310 #define ADC_Channel_8 ((uint8_t)0x08)
311 #define ADC_Channel_9 ((uint8_t)0x09)
312 #define ADC_Channel_10 ((uint8_t)0x0A)
313 #define ADC_Channel_11 ((uint8_t)0x0B)
314 #define ADC_Channel_12 ((uint8_t)0x0C)
315 #define ADC_Channel_13 ((uint8_t)0x0D)
316 #define ADC_Channel_14 ((uint8_t)0x0E)
317 #define ADC_Channel_15 ((uint8_t)0x0F)
318 #define ADC_Channel_16 ((uint8_t)0x10)
319 #define ADC_Channel_17 ((uint8_t)0x11)
320 #define ADC_Channel_18 ((uint8_t)0x12)
321 
322 #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
323 #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
324 #define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
325 
326 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
327  ((CHANNEL) == ADC_Channel_1) || \
328  ((CHANNEL) == ADC_Channel_2) || \
329  ((CHANNEL) == ADC_Channel_3) || \
330  ((CHANNEL) == ADC_Channel_4) || \
331  ((CHANNEL) == ADC_Channel_5) || \
332  ((CHANNEL) == ADC_Channel_6) || \
333  ((CHANNEL) == ADC_Channel_7) || \
334  ((CHANNEL) == ADC_Channel_8) || \
335  ((CHANNEL) == ADC_Channel_9) || \
336  ((CHANNEL) == ADC_Channel_10) || \
337  ((CHANNEL) == ADC_Channel_11) || \
338  ((CHANNEL) == ADC_Channel_12) || \
339  ((CHANNEL) == ADC_Channel_13) || \
340  ((CHANNEL) == ADC_Channel_14) || \
341  ((CHANNEL) == ADC_Channel_15) || \
342  ((CHANNEL) == ADC_Channel_16) || \
343  ((CHANNEL) == ADC_Channel_17) || \
344  ((CHANNEL) == ADC_Channel_18))
345 /**
346  * @}
347  */
348 
349 
350 /** @defgroup ADC_sampling_times
351  * @{
352  */
353 #define ADC_SampleTime_3Cycles ((uint8_t)0x00)
354 #define ADC_SampleTime_15Cycles ((uint8_t)0x01)
355 #define ADC_SampleTime_28Cycles ((uint8_t)0x02)
356 #define ADC_SampleTime_56Cycles ((uint8_t)0x03)
357 #define ADC_SampleTime_84Cycles ((uint8_t)0x04)
358 #define ADC_SampleTime_112Cycles ((uint8_t)0x05)
359 #define ADC_SampleTime_144Cycles ((uint8_t)0x06)
360 #define ADC_SampleTime_480Cycles ((uint8_t)0x07)
361 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
362  ((TIME) == ADC_SampleTime_15Cycles) || \
363  ((TIME) == ADC_SampleTime_28Cycles) || \
364  ((TIME) == ADC_SampleTime_56Cycles) || \
365  ((TIME) == ADC_SampleTime_84Cycles) || \
366  ((TIME) == ADC_SampleTime_112Cycles) || \
367  ((TIME) == ADC_SampleTime_144Cycles) || \
368  ((TIME) == ADC_SampleTime_480Cycles))
369 /**
370  * @}
371  */
372 
373 
374 /** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
375  * @{
376  */
377 #define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
378 #define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
379 #define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
380 #define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
381 #define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
382  ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
383  ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
384  ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
385 
386 /**
387  * @}
388  */
389 
390 
391 /** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion
392  * @{
393  */
394 #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000)
395 #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000)
396 #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000)
397 #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000)
398 #define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000)
399 #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000)
400 #define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
401 #define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
402 #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
403 #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000)
404 #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000)
405 #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000)
406 #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000)
407 #define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000)
408 #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000)
409 #define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
410 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
411  ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
412  ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
413  ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
414  ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
415  ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
416  ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
417  ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
418  ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
419  ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
420  ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
421  ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
422  ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
423  ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
424  ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
425  ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
426 /**
427  * @}
428  */
429 
430 
431 /** @defgroup ADC_injected_channel_selection
432  * @{
433  */
434 #define ADC_InjectedChannel_1 ((uint8_t)0x14)
435 #define ADC_InjectedChannel_2 ((uint8_t)0x18)
436 #define ADC_InjectedChannel_3 ((uint8_t)0x1C)
437 #define ADC_InjectedChannel_4 ((uint8_t)0x20)
438 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
439  ((CHANNEL) == ADC_InjectedChannel_2) || \
440  ((CHANNEL) == ADC_InjectedChannel_3) || \
441  ((CHANNEL) == ADC_InjectedChannel_4))
442 /**
443  * @}
444  */
445 
446 
447 /** @defgroup ADC_analog_watchdog_selection
448  * @{
449  */
450 #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
451 #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
452 #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
453 #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
454 #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
455 #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
456 #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
457 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
458  ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
459  ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
460  ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
461  ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
462  ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
463  ((WATCHDOG) == ADC_AnalogWatchdog_None))
464 /**
465  * @}
466  */
467 
468 
469 /** @defgroup ADC_interrupts_definition
470  * @{
471  */
472 #define ADC_IT_EOC ((uint16_t)0x0205)
473 #define ADC_IT_AWD ((uint16_t)0x0106)
474 #define ADC_IT_JEOC ((uint16_t)0x0407)
475 #define ADC_IT_OVR ((uint16_t)0x201A)
476 #define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
477  ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
478 /**
479  * @}
480  */
481 
482 
483 /** @defgroup ADC_flags_definition
484  * @{
485  */
486 #define ADC_FLAG_AWD ((uint8_t)0x01)
487 #define ADC_FLAG_EOC ((uint8_t)0x02)
488 #define ADC_FLAG_JEOC ((uint8_t)0x04)
489 #define ADC_FLAG_JSTRT ((uint8_t)0x08)
490 #define ADC_FLAG_STRT ((uint8_t)0x10)
491 #define ADC_FLAG_OVR ((uint8_t)0x20)
492 
493 #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))
494 #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
495  ((FLAG) == ADC_FLAG_EOC) || \
496  ((FLAG) == ADC_FLAG_JEOC) || \
497  ((FLAG)== ADC_FLAG_JSTRT) || \
498  ((FLAG) == ADC_FLAG_STRT) || \
499  ((FLAG)== ADC_FLAG_OVR))
500 /**
501  * @}
502  */
503 
504 
505 /** @defgroup ADC_thresholds
506  * @{
507  */
508 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
509 /**
510  * @}
511  */
512 
513 
514 /** @defgroup ADC_injected_offset
515  * @{
516  */
517 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
518 /**
519  * @}
520  */
521 
522 
523 /** @defgroup ADC_injected_length
524  * @{
525  */
526 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
527 /**
528  * @}
529  */
530 
531 
532 /** @defgroup ADC_injected_rank
533  * @{
534  */
535 #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
536 /**
537  * @}
538  */
539 
540 
541 /** @defgroup ADC_regular_length
542  * @{
543  */
544 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
545 /**
546  * @}
547  */
548 
549 
550 /** @defgroup ADC_regular_rank
551  * @{
552  */
553 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
554 /**
555  * @}
556  */
557 
558 
559 /** @defgroup ADC_regular_discontinuous_mode_number
560  * @{
561  */
562 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
563 /**
564  * @}
565  */
566 
567 
568 /**
569  * @}
570  */
571 
572 /* Exported macro ------------------------------------------------------------*/
573 /* Exported functions --------------------------------------------------------*/
574 
575 /* Function used to set the ADC configuration to the default reset state *****/
576 void ADC_DeInit(void);
577 
578 /* Initialization and Configuration functions *********************************/
579 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
580 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
581 void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
582 void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
583 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
584 
585 /* Analog Watchdog configuration functions ************************************/
586 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
587 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
588 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
589 
590 /* Temperature Sensor, Vrefint and VBAT management functions ******************/
591 void ADC_TempSensorVrefintCmd(FunctionalState NewState);
592 void ADC_VBATCmd(FunctionalState NewState);
593 
594 /* Regular Channels Configuration functions ***********************************/
595 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
596 void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
597 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
598 void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
599 void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
600 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
601 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
602 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
603 uint32_t ADC_GetMultiModeConversionValue(void);
604 
605 /* Regular Channels DMA Configuration functions *******************************/
606 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
607 void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
608 void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
609 
610 /* Injected channels Configuration functions **********************************/
611 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
612 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
613 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
614 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
615 void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
616 void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
617 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
618 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
619 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
620 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
621 
622 /* Interrupts and flags management functions **********************************/
623 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
624 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
625 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
626 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
627 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
628 
629 #ifdef __cplusplus
630 }
631 #endif
632 
633 #endif /*__STM32F4xx_ADC_H */
634 
635 /**
636  * @}
637  */
638 
639 /**
640  * @}
641  */
642 
643 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
ADC_CommonInitTypeDef::ADC_Prescaler
uint32_t ADC_Prescaler
Definition: stm32f4xx_adc.h:83
ADC_InitTypeDef::ADC_ExternalTrigConv
uint32_t ADC_ExternalTrigConv
Definition: stm32f4xx_adc.h:62
ADC_InitTypeDef
ADC Init structure definition.
Definition: stm32f4xx_adc.h:47
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f4xx.h:293
ADC_InitTypeDef::ADC_ContinuousConvMode
FunctionalState ADC_ContinuousConvMode
Definition: stm32f4xx_adc.h:55
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
ADC_CommonInitTypeDef
ADC Common Init structure definition.
Definition: stm32f4xx_adc.h:78
ADC_InitTypeDef::ADC_DataAlign
uint32_t ADC_DataAlign
Definition: stm32f4xx_adc.h:66
ADC_CommonInitTypeDef::ADC_Mode
uint32_t ADC_Mode
Definition: stm32f4xx_adc.h:80
ADC_InitTypeDef::ADC_NbrOfConversion
uint8_t ADC_NbrOfConversion
Definition: stm32f4xx_adc.h:69
ADC_CommonInitTypeDef::ADC_TwoSamplingDelay
uint32_t ADC_TwoSamplingDelay
Definition: stm32f4xx_adc.h:90
ADC_InitTypeDef::ADC_ScanConvMode
FunctionalState ADC_ScanConvMode
Definition: stm32f4xx_adc.h:51
ADC_CommonInitTypeDef::ADC_DMAAccessMode
uint32_t ADC_DMAAccessMode
Definition: stm32f4xx_adc.h:86
ADC_InitTypeDef::ADC_Resolution
uint32_t ADC_Resolution
Definition: stm32f4xx_adc.h:49
ADC_InitTypeDef::ADC_ExternalTrigConvEdge
uint32_t ADC_ExternalTrigConvEdge
Definition: stm32f4xx_adc.h:58
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