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stm32f4xx_tim.h
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1 /**
2  ******************************************************************************
3  * @file stm32f4xx_tim.h
4  * @author MCD Application Team
5  * @version V1.0.0
6  * @date 30-September-2011
7  * @brief This file contains all the functions prototypes for the TIM firmware
8  * library.
9  ******************************************************************************
10  * @attention
11  *
12  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18  *
19  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
20  ******************************************************************************
21  */
22 
23 /* Define to prevent recursive inclusion -------------------------------------*/
24 #ifndef __STM32F4xx_TIM_H
25 #define __STM32F4xx_TIM_H
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 /* Includes ------------------------------------------------------------------*/
32 #include "stm32/stm32f4xx.h"
33 
34 /** @addtogroup STM32F4xx_StdPeriph_Driver
35  * @{
36  */
37 
38 /** @addtogroup TIM
39  * @{
40  */
41 
42 /* Exported types ------------------------------------------------------------*/
43 
44 /**
45  * @brief TIM Time Base Init structure definition
46  * @note This structure is used with all TIMx except for TIM6 and TIM7.
47  */
48 
49 typedef struct
50 {
51  uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
52  This parameter can be a number between 0x0000 and 0xFFFF */
53 
54  uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
55  This parameter can be a value of @ref TIM_Counter_Mode */
56 
57  uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
58  Auto-Reload Register at the next update event.
59  This parameter must be a number between 0x0000 and 0xFFFF. */
60 
61  uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
62  This parameter can be a value of @ref TIM_Clock_Division_CKD */
63 
64  uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
65  reaches zero, an update event is generated and counting restarts
66  from the RCR value (N).
67  This means in PWM mode that (N+1) corresponds to:
68  - the number of PWM periods in edge-aligned mode
69  - the number of half PWM period in center-aligned mode
70  This parameter must be a number between 0x00 and 0xFF.
71  @note This parameter is valid only for TIM1 and TIM8. */
72 } TIM_TimeBaseInitTypeDef;
73 
74 /**
75  * @brief TIM Output Compare Init structure definition
76  */
77 
78 typedef struct
79 {
80  uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
81  This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
82 
83  uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
84  This parameter can be a value of @ref TIM_Output_Compare_State */
85 
86  uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
87  This parameter can be a value of @ref TIM_Output_Compare_N_State
88  @note This parameter is valid only for TIM1 and TIM8. */
89 
90  uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
91  This parameter can be a number between 0x0000 and 0xFFFF */
92 
93  uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
94  This parameter can be a value of @ref TIM_Output_Compare_Polarity */
95 
96  uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
97  This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
98  @note This parameter is valid only for TIM1 and TIM8. */
99 
100  uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
101  This parameter can be a value of @ref TIM_Output_Compare_Idle_State
102  @note This parameter is valid only for TIM1 and TIM8. */
103 
104  uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
105  This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
106  @note This parameter is valid only for TIM1 and TIM8. */
107 } TIM_OCInitTypeDef;
108 
109 /**
110  * @brief TIM Input Capture Init structure definition
111  */
112 
113 typedef struct
114 {
115 
116  uint16_t TIM_Channel; /*!< Specifies the TIM channel.
117  This parameter can be a value of @ref TIM_Channel */
118 
119  uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
120  This parameter can be a value of @ref TIM_Input_Capture_Polarity */
121 
122  uint16_t TIM_ICSelection; /*!< Specifies the input.
123  This parameter can be a value of @ref TIM_Input_Capture_Selection */
124 
125  uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
126  This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
127 
128  uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
129  This parameter can be a number between 0x0 and 0xF */
130 } TIM_ICInitTypeDef;
131 
132 /**
133  * @brief BDTR structure definition
134  * @note This structure is used only with TIM1 and TIM8.
135  */
136 
137 typedef struct
138 {
139 
140  uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
141  This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
142 
143  uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
144  This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
145 
146  uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
147  This parameter can be a value of @ref TIM_Lock_level */
148 
149  uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
150  switching-on of the outputs.
151  This parameter can be a number between 0x00 and 0xFF */
152 
153  uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
154  This parameter can be a value of @ref TIM_Break_Input_enable_disable */
155 
156  uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
157  This parameter can be a value of @ref TIM_Break_Polarity */
158 
159  uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
160  This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
161 } TIM_BDTRInitTypeDef;
162 
163 /* Exported constants --------------------------------------------------------*/
164 
165 /** @defgroup TIM_Exported_constants
166  * @{
167  */
168 
169 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
170  ((PERIPH) == TIM2) || \
171  ((PERIPH) == TIM3) || \
172  ((PERIPH) == TIM4) || \
173  ((PERIPH) == TIM5) || \
174  ((PERIPH) == TIM6) || \
175  ((PERIPH) == TIM7) || \
176  ((PERIPH) == TIM8) || \
177  ((PERIPH) == TIM9) || \
178  ((PERIPH) == TIM10) || \
179  ((PERIPH) == TIM11) || \
180  ((PERIPH) == TIM12) || \
181  (((PERIPH) == TIM13) || \
182  ((PERIPH) == TIM14)))
183 /* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */
184 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
185  ((PERIPH) == TIM2) || \
186  ((PERIPH) == TIM3) || \
187  ((PERIPH) == TIM4) || \
188  ((PERIPH) == TIM5) || \
189  ((PERIPH) == TIM8) || \
190  ((PERIPH) == TIM9) || \
191  ((PERIPH) == TIM10) || \
192  ((PERIPH) == TIM11) || \
193  ((PERIPH) == TIM12) || \
194  ((PERIPH) == TIM13) || \
195  ((PERIPH) == TIM14))
196 
197 /* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */
198 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
199  ((PERIPH) == TIM2) || \
200  ((PERIPH) == TIM3) || \
201  ((PERIPH) == TIM4) || \
202  ((PERIPH) == TIM5) || \
203  ((PERIPH) == TIM8) || \
204  ((PERIPH) == TIM9) || \
205  ((PERIPH) == TIM12))
206 /* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */
207 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
208  ((PERIPH) == TIM2) || \
209  ((PERIPH) == TIM3) || \
210  ((PERIPH) == TIM4) || \
211  ((PERIPH) == TIM5) || \
212  ((PERIPH) == TIM8))
213 /* LIST4: TIM1 and TIM8 */
214 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
215  ((PERIPH) == TIM8))
216 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
217 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
218  ((PERIPH) == TIM2) || \
219  ((PERIPH) == TIM3) || \
220  ((PERIPH) == TIM4) || \
221  ((PERIPH) == TIM5) || \
222  ((PERIPH) == TIM6) || \
223  ((PERIPH) == TIM7) || \
224  ((PERIPH) == TIM8))
225 /* LIST6: TIM2, TIM5 and TIM11 */
226 #define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \
227  ((TIMx) == TIM5) || \
228  ((TIMx) == TIM11))
229 
230 /** @defgroup TIM_Output_Compare_and_PWM_modes
231  * @{
232  */
233 
234 #define TIM_OCMode_Timing ((uint16_t)0x0000)
235 #define TIM_OCMode_Active ((uint16_t)0x0010)
236 #define TIM_OCMode_Inactive ((uint16_t)0x0020)
237 #define TIM_OCMode_Toggle ((uint16_t)0x0030)
238 #define TIM_OCMode_PWM1 ((uint16_t)0x0060)
239 #define TIM_OCMode_PWM2 ((uint16_t)0x0070)
240 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
241  ((MODE) == TIM_OCMode_Active) || \
242  ((MODE) == TIM_OCMode_Inactive) || \
243  ((MODE) == TIM_OCMode_Toggle)|| \
244  ((MODE) == TIM_OCMode_PWM1) || \
245  ((MODE) == TIM_OCMode_PWM2))
246 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
247  ((MODE) == TIM_OCMode_Active) || \
248  ((MODE) == TIM_OCMode_Inactive) || \
249  ((MODE) == TIM_OCMode_Toggle)|| \
250  ((MODE) == TIM_OCMode_PWM1) || \
251  ((MODE) == TIM_OCMode_PWM2) || \
252  ((MODE) == TIM_ForcedAction_Active) || \
253  ((MODE) == TIM_ForcedAction_InActive))
254 /**
255  * @}
256  */
257 
258 /** @defgroup TIM_One_Pulse_Mode
259  * @{
260  */
261 
262 #define TIM_OPMode_Single ((uint16_t)0x0008)
263 #define TIM_OPMode_Repetitive ((uint16_t)0x0000)
264 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
265  ((MODE) == TIM_OPMode_Repetitive))
266 /**
267  * @}
268  */
269 
270 /** @defgroup TIM_Channel
271  * @{
272  */
273 
274 #define TIM_Channel_1 ((uint16_t)0x0000)
275 #define TIM_Channel_2 ((uint16_t)0x0004)
276 #define TIM_Channel_3 ((uint16_t)0x0008)
277 #define TIM_Channel_4 ((uint16_t)0x000C)
278 
279 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
280  ((CHANNEL) == TIM_Channel_2) || \
281  ((CHANNEL) == TIM_Channel_3) || \
282  ((CHANNEL) == TIM_Channel_4))
283 
284 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
285  ((CHANNEL) == TIM_Channel_2))
286 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
287  ((CHANNEL) == TIM_Channel_2) || \
288  ((CHANNEL) == TIM_Channel_3))
289 /**
290  * @}
291  */
292 
293 /** @defgroup TIM_Clock_Division_CKD
294  * @{
295  */
296 
297 #define TIM_CKD_DIV1 ((uint16_t)0x0000)
298 #define TIM_CKD_DIV2 ((uint16_t)0x0100)
299 #define TIM_CKD_DIV4 ((uint16_t)0x0200)
300 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
301  ((DIV) == TIM_CKD_DIV2) || \
302  ((DIV) == TIM_CKD_DIV4))
303 /**
304  * @}
305  */
306 
307 /** @defgroup TIM_Counter_Mode
308  * @{
309  */
310 
311 #define TIM_CounterMode_Up ((uint16_t)0x0000)
312 #define TIM_CounterMode_Down ((uint16_t)0x0010)
313 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
314 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
315 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
316 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
317  ((MODE) == TIM_CounterMode_Down) || \
318  ((MODE) == TIM_CounterMode_CenterAligned1) || \
319  ((MODE) == TIM_CounterMode_CenterAligned2) || \
320  ((MODE) == TIM_CounterMode_CenterAligned3))
321 /**
322  * @}
323  */
324 
325 /** @defgroup TIM_Output_Compare_Polarity
326  * @{
327  */
328 
329 #define TIM_OCPolarity_High ((uint16_t)0x0000)
330 #define TIM_OCPolarity_Low ((uint16_t)0x0002)
331 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
332  ((POLARITY) == TIM_OCPolarity_Low))
333 /**
334  * @}
335  */
336 
337 /** @defgroup TIM_Output_Compare_N_Polarity
338  * @{
339  */
340 
341 #define TIM_OCNPolarity_High ((uint16_t)0x0000)
342 #define TIM_OCNPolarity_Low ((uint16_t)0x0008)
343 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
344  ((POLARITY) == TIM_OCNPolarity_Low))
345 /**
346  * @}
347  */
348 
349 /** @defgroup TIM_Output_Compare_State
350  * @{
351  */
352 
353 #define TIM_OutputState_Disable ((uint16_t)0x0000)
354 #define TIM_OutputState_Enable ((uint16_t)0x0001)
355 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
356  ((STATE) == TIM_OutputState_Enable))
357 /**
358  * @}
359  */
360 
361 /** @defgroup TIM_Output_Compare_N_State
362  * @{
363  */
364 
365 #define TIM_OutputNState_Disable ((uint16_t)0x0000)
366 #define TIM_OutputNState_Enable ((uint16_t)0x0004)
367 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
368  ((STATE) == TIM_OutputNState_Enable))
369 /**
370  * @}
371  */
372 
373 /** @defgroup TIM_Capture_Compare_State
374  * @{
375  */
376 
377 #define TIM_CCx_Enable ((uint16_t)0x0001)
378 #define TIM_CCx_Disable ((uint16_t)0x0000)
379 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
380  ((CCX) == TIM_CCx_Disable))
381 /**
382  * @}
383  */
384 
385 /** @defgroup TIM_Capture_Compare_N_State
386  * @{
387  */
388 
389 #define TIM_CCxN_Enable ((uint16_t)0x0004)
390 #define TIM_CCxN_Disable ((uint16_t)0x0000)
391 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
392  ((CCXN) == TIM_CCxN_Disable))
393 /**
394  * @}
395  */
396 
397 /** @defgroup TIM_Break_Input_enable_disable
398  * @{
399  */
400 
401 #define TIM_Break_Enable ((uint16_t)0x1000)
402 #define TIM_Break_Disable ((uint16_t)0x0000)
403 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
404  ((STATE) == TIM_Break_Disable))
405 /**
406  * @}
407  */
408 
409 /** @defgroup TIM_Break_Polarity
410  * @{
411  */
412 
413 #define TIM_BreakPolarity_Low ((uint16_t)0x0000)
414 #define TIM_BreakPolarity_High ((uint16_t)0x2000)
415 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
416  ((POLARITY) == TIM_BreakPolarity_High))
417 /**
418  * @}
419  */
420 
421 /** @defgroup TIM_AOE_Bit_Set_Reset
422  * @{
423  */
424 
425 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
426 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
427 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
428  ((STATE) == TIM_AutomaticOutput_Disable))
429 /**
430  * @}
431  */
432 
433 /** @defgroup TIM_Lock_level
434  * @{
435  */
436 
437 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
438 #define TIM_LOCKLevel_1 ((uint16_t)0x0100)
439 #define TIM_LOCKLevel_2 ((uint16_t)0x0200)
440 #define TIM_LOCKLevel_3 ((uint16_t)0x0300)
441 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
442  ((LEVEL) == TIM_LOCKLevel_1) || \
443  ((LEVEL) == TIM_LOCKLevel_2) || \
444  ((LEVEL) == TIM_LOCKLevel_3))
445 /**
446  * @}
447  */
448 
449 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
450  * @{
451  */
452 
453 #define TIM_OSSIState_Enable ((uint16_t)0x0400)
454 #define TIM_OSSIState_Disable ((uint16_t)0x0000)
455 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
456  ((STATE) == TIM_OSSIState_Disable))
457 /**
458  * @}
459  */
460 
461 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
462  * @{
463  */
464 
465 #define TIM_OSSRState_Enable ((uint16_t)0x0800)
466 #define TIM_OSSRState_Disable ((uint16_t)0x0000)
467 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
468  ((STATE) == TIM_OSSRState_Disable))
469 /**
470  * @}
471  */
472 
473 /** @defgroup TIM_Output_Compare_Idle_State
474  * @{
475  */
476 
477 #define TIM_OCIdleState_Set ((uint16_t)0x0100)
478 #define TIM_OCIdleState_Reset ((uint16_t)0x0000)
479 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
480  ((STATE) == TIM_OCIdleState_Reset))
481 /**
482  * @}
483  */
484 
485 /** @defgroup TIM_Output_Compare_N_Idle_State
486  * @{
487  */
488 
489 #define TIM_OCNIdleState_Set ((uint16_t)0x0200)
490 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
491 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
492  ((STATE) == TIM_OCNIdleState_Reset))
493 /**
494  * @}
495  */
496 
497 /** @defgroup TIM_Input_Capture_Polarity
498  * @{
499  */
500 
501 #define TIM_ICPolarity_Rising ((uint16_t)0x0000)
502 #define TIM_ICPolarity_Falling ((uint16_t)0x0002)
503 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
504 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
505  ((POLARITY) == TIM_ICPolarity_Falling)|| \
506  ((POLARITY) == TIM_ICPolarity_BothEdge))
507 /**
508  * @}
509  */
510 
511 /** @defgroup TIM_Input_Capture_Selection
512  * @{
513  */
514 
515 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
516  connected to IC1, IC2, IC3 or IC4, respectively */
517 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
518  connected to IC2, IC1, IC4 or IC3, respectively. */
519 #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
520 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
521  ((SELECTION) == TIM_ICSelection_IndirectTI) || \
522  ((SELECTION) == TIM_ICSelection_TRC))
523 /**
524  * @}
525  */
526 
527 /** @defgroup TIM_Input_Capture_Prescaler
528  * @{
529  */
530 
531 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
532 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
533 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
534 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
535 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
536  ((PRESCALER) == TIM_ICPSC_DIV2) || \
537  ((PRESCALER) == TIM_ICPSC_DIV4) || \
538  ((PRESCALER) == TIM_ICPSC_DIV8))
539 /**
540  * @}
541  */
542 
543 /** @defgroup TIM_interrupt_sources
544  * @{
545  */
546 
547 #define TIM_IT_Update ((uint16_t)0x0001)
548 #define TIM_IT_CC1 ((uint16_t)0x0002)
549 #define TIM_IT_CC2 ((uint16_t)0x0004)
550 #define TIM_IT_CC3 ((uint16_t)0x0008)
551 #define TIM_IT_CC4 ((uint16_t)0x0010)
552 #define TIM_IT_COM ((uint16_t)0x0020)
553 #define TIM_IT_Trigger ((uint16_t)0x0040)
554 #define TIM_IT_Break ((uint16_t)0x0080)
555 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
556 
557 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
558  ((IT) == TIM_IT_CC1) || \
559  ((IT) == TIM_IT_CC2) || \
560  ((IT) == TIM_IT_CC3) || \
561  ((IT) == TIM_IT_CC4) || \
562  ((IT) == TIM_IT_COM) || \
563  ((IT) == TIM_IT_Trigger) || \
564  ((IT) == TIM_IT_Break))
565 /**
566  * @}
567  */
568 
569 /** @defgroup TIM_DMA_Base_address
570  * @{
571  */
572 
573 #define TIM_DMABase_CR1 ((uint16_t)0x0000)
574 #define TIM_DMABase_CR2 ((uint16_t)0x0001)
575 #define TIM_DMABase_SMCR ((uint16_t)0x0002)
576 #define TIM_DMABase_DIER ((uint16_t)0x0003)
577 #define TIM_DMABase_SR ((uint16_t)0x0004)
578 #define TIM_DMABase_EGR ((uint16_t)0x0005)
579 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
580 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
581 #define TIM_DMABase_CCER ((uint16_t)0x0008)
582 #define TIM_DMABase_CNT ((uint16_t)0x0009)
583 #define TIM_DMABase_PSC ((uint16_t)0x000A)
584 #define TIM_DMABase_ARR ((uint16_t)0x000B)
585 #define TIM_DMABase_RCR ((uint16_t)0x000C)
586 #define TIM_DMABase_CCR1 ((uint16_t)0x000D)
587 #define TIM_DMABase_CCR2 ((uint16_t)0x000E)
588 #define TIM_DMABase_CCR3 ((uint16_t)0x000F)
589 #define TIM_DMABase_CCR4 ((uint16_t)0x0010)
590 #define TIM_DMABase_BDTR ((uint16_t)0x0011)
591 #define TIM_DMABase_DCR ((uint16_t)0x0012)
592 #define TIM_DMABase_OR ((uint16_t)0x0013)
593 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
594  ((BASE) == TIM_DMABase_CR2) || \
595  ((BASE) == TIM_DMABase_SMCR) || \
596  ((BASE) == TIM_DMABase_DIER) || \
597  ((BASE) == TIM_DMABase_SR) || \
598  ((BASE) == TIM_DMABase_EGR) || \
599  ((BASE) == TIM_DMABase_CCMR1) || \
600  ((BASE) == TIM_DMABase_CCMR2) || \
601  ((BASE) == TIM_DMABase_CCER) || \
602  ((BASE) == TIM_DMABase_CNT) || \
603  ((BASE) == TIM_DMABase_PSC) || \
604  ((BASE) == TIM_DMABase_ARR) || \
605  ((BASE) == TIM_DMABase_RCR) || \
606  ((BASE) == TIM_DMABase_CCR1) || \
607  ((BASE) == TIM_DMABase_CCR2) || \
608  ((BASE) == TIM_DMABase_CCR3) || \
609  ((BASE) == TIM_DMABase_CCR4) || \
610  ((BASE) == TIM_DMABase_BDTR) || \
611  ((BASE) == TIM_DMABase_DCR) || \
612  ((BASE) == TIM_DMABase_OR))
613 /**
614  * @}
615  */
616 
617 /** @defgroup TIM_DMA_Burst_Length
618  * @{
619  */
620 
621 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
622 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
623 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
624 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
625 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
626 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
627 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
628 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
629 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
630 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
631 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
632 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
633 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
634 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
635 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
636 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
637 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
638 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
639 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
640  ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
641  ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
642  ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
643  ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
644  ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
645  ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
646  ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
647  ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
648  ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
649  ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
650  ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
651  ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
652  ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
653  ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
654  ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
655  ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
656  ((LENGTH) == TIM_DMABurstLength_18Transfers))
657 /**
658  * @}
659  */
660 
661 /** @defgroup TIM_DMA_sources
662  * @{
663  */
664 
665 #define TIM_DMA_Update ((uint16_t)0x0100)
666 #define TIM_DMA_CC1 ((uint16_t)0x0200)
667 #define TIM_DMA_CC2 ((uint16_t)0x0400)
668 #define TIM_DMA_CC3 ((uint16_t)0x0800)
669 #define TIM_DMA_CC4 ((uint16_t)0x1000)
670 #define TIM_DMA_COM ((uint16_t)0x2000)
671 #define TIM_DMA_Trigger ((uint16_t)0x4000)
672 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
673 
674 /**
675  * @}
676  */
677 
678 /** @defgroup TIM_External_Trigger_Prescaler
679  * @{
680  */
681 
682 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
683 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
684 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
685 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
686 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
687  ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
688  ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
689  ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
690 /**
691  * @}
692  */
693 
694 /** @defgroup TIM_Internal_Trigger_Selection
695  * @{
696  */
697 
698 #define TIM_TS_ITR0 ((uint16_t)0x0000)
699 #define TIM_TS_ITR1 ((uint16_t)0x0010)
700 #define TIM_TS_ITR2 ((uint16_t)0x0020)
701 #define TIM_TS_ITR3 ((uint16_t)0x0030)
702 #define TIM_TS_TI1F_ED ((uint16_t)0x0040)
703 #define TIM_TS_TI1FP1 ((uint16_t)0x0050)
704 #define TIM_TS_TI2FP2 ((uint16_t)0x0060)
705 #define TIM_TS_ETRF ((uint16_t)0x0070)
706 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
707  ((SELECTION) == TIM_TS_ITR1) || \
708  ((SELECTION) == TIM_TS_ITR2) || \
709  ((SELECTION) == TIM_TS_ITR3) || \
710  ((SELECTION) == TIM_TS_TI1F_ED) || \
711  ((SELECTION) == TIM_TS_TI1FP1) || \
712  ((SELECTION) == TIM_TS_TI2FP2) || \
713  ((SELECTION) == TIM_TS_ETRF))
714 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
715  ((SELECTION) == TIM_TS_ITR1) || \
716  ((SELECTION) == TIM_TS_ITR2) || \
717  ((SELECTION) == TIM_TS_ITR3))
718 /**
719  * @}
720  */
721 
722 /** @defgroup TIM_TIx_External_Clock_Source
723  * @{
724  */
725 
726 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
727 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
728 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
729 
730 /**
731  * @}
732  */
733 
734 /** @defgroup TIM_External_Trigger_Polarity
735  * @{
736  */
737 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
738 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
739 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
740  ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
741 /**
742  * @}
743  */
744 
745 /** @defgroup TIM_Prescaler_Reload_Mode
746  * @{
747  */
748 
749 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
750 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
751 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
752  ((RELOAD) == TIM_PSCReloadMode_Immediate))
753 /**
754  * @}
755  */
756 
757 /** @defgroup TIM_Forced_Action
758  * @{
759  */
760 
761 #define TIM_ForcedAction_Active ((uint16_t)0x0050)
762 #define TIM_ForcedAction_InActive ((uint16_t)0x0040)
763 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
764  ((ACTION) == TIM_ForcedAction_InActive))
765 /**
766  * @}
767  */
768 
769 /** @defgroup TIM_Encoder_Mode
770  * @{
771  */
772 
773 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
774 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
775 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
776 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
777  ((MODE) == TIM_EncoderMode_TI2) || \
778  ((MODE) == TIM_EncoderMode_TI12))
779 /**
780  * @}
781  */
782 
783 
784 /** @defgroup TIM_Event_Source
785  * @{
786  */
787 
788 #define TIM_EventSource_Update ((uint16_t)0x0001)
789 #define TIM_EventSource_CC1 ((uint16_t)0x0002)
790 #define TIM_EventSource_CC2 ((uint16_t)0x0004)
791 #define TIM_EventSource_CC3 ((uint16_t)0x0008)
792 #define TIM_EventSource_CC4 ((uint16_t)0x0010)
793 #define TIM_EventSource_COM ((uint16_t)0x0020)
794 #define TIM_EventSource_Trigger ((uint16_t)0x0040)
795 #define TIM_EventSource_Break ((uint16_t)0x0080)
796 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
797 
798 /**
799  * @}
800  */
801 
802 /** @defgroup TIM_Update_Source
803  * @{
804  */
805 
806 #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
807  or the setting of UG bit, or an update generation
808  through the slave mode controller. */
809 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
810 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
811  ((SOURCE) == TIM_UpdateSource_Regular))
812 /**
813  * @}
814  */
815 
816 /** @defgroup TIM_Output_Compare_Preload_State
817  * @{
818  */
819 
820 #define TIM_OCPreload_Enable ((uint16_t)0x0008)
821 #define TIM_OCPreload_Disable ((uint16_t)0x0000)
822 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
823  ((STATE) == TIM_OCPreload_Disable))
824 /**
825  * @}
826  */
827 
828 /** @defgroup TIM_Output_Compare_Fast_State
829  * @{
830  */
831 
832 #define TIM_OCFast_Enable ((uint16_t)0x0004)
833 #define TIM_OCFast_Disable ((uint16_t)0x0000)
834 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
835  ((STATE) == TIM_OCFast_Disable))
836 
837 /**
838  * @}
839  */
840 
841 /** @defgroup TIM_Output_Compare_Clear_State
842  * @{
843  */
844 
845 #define TIM_OCClear_Enable ((uint16_t)0x0080)
846 #define TIM_OCClear_Disable ((uint16_t)0x0000)
847 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
848  ((STATE) == TIM_OCClear_Disable))
849 /**
850  * @}
851  */
852 
853 /** @defgroup TIM_Trigger_Output_Source
854  * @{
855  */
856 
857 #define TIM_TRGOSource_Reset ((uint16_t)0x0000)
858 #define TIM_TRGOSource_Enable ((uint16_t)0x0010)
859 #define TIM_TRGOSource_Update ((uint16_t)0x0020)
860 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
861 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
862 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
863 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
864 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
865 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
866  ((SOURCE) == TIM_TRGOSource_Enable) || \
867  ((SOURCE) == TIM_TRGOSource_Update) || \
868  ((SOURCE) == TIM_TRGOSource_OC1) || \
869  ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
870  ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
871  ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
872  ((SOURCE) == TIM_TRGOSource_OC4Ref))
873 /**
874  * @}
875  */
876 
877 /** @defgroup TIM_Slave_Mode
878  * @{
879  */
880 
881 #define TIM_SlaveMode_Reset ((uint16_t)0x0004)
882 #define TIM_SlaveMode_Gated ((uint16_t)0x0005)
883 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
884 #define TIM_SlaveMode_External1 ((uint16_t)0x0007)
885 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
886  ((MODE) == TIM_SlaveMode_Gated) || \
887  ((MODE) == TIM_SlaveMode_Trigger) || \
888  ((MODE) == TIM_SlaveMode_External1))
889 /**
890  * @}
891  */
892 
893 /** @defgroup TIM_Master_Slave_Mode
894  * @{
895  */
896 
897 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
898 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
899 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
900  ((STATE) == TIM_MasterSlaveMode_Disable))
901 /**
902  * @}
903  */
904 /** @defgroup TIM_Remap
905  * @{
906  */
907 
908 #define TIM2_TIM8_TRGO ((uint16_t)0x0000)
909 #define TIM2_ETH_PTP ((uint16_t)0x0400)
910 #define TIM2_USBFS_SOF ((uint16_t)0x0800)
911 #define TIM2_USBHS_SOF ((uint16_t)0x0C00)
912 
913 #define TIM5_GPIO ((uint16_t)0x0000)
914 #define TIM5_LSI ((uint16_t)0x0040)
915 #define TIM5_LSE ((uint16_t)0x0080)
916 #define TIM5_RTC ((uint16_t)0x00C0)
917 
918 #define TIM11_GPIO ((uint16_t)0x0000)
919 #define TIM11_HSE ((uint16_t)0x0002)
920 
921 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\
922  ((TIM_REMAP) == TIM2_ETH_PTP)||\
923  ((TIM_REMAP) == TIM2_USBFS_SOF)||\
924  ((TIM_REMAP) == TIM2_USBHS_SOF)||\
925  ((TIM_REMAP) == TIM5_GPIO)||\
926  ((TIM_REMAP) == TIM5_LSI)||\
927  ((TIM_REMAP) == TIM5_LSE)||\
928  ((TIM_REMAP) == TIM5_RTC)||\
929  ((TIM_REMAP) == TIM11_GPIO)||\
930  ((TIM_REMAP) == TIM11_HSE))
931 
932 /**
933  * @}
934  */
935 /** @defgroup TIM_Flags
936  * @{
937  */
938 
939 #define TIM_FLAG_Update ((uint16_t)0x0001)
940 #define TIM_FLAG_CC1 ((uint16_t)0x0002)
941 #define TIM_FLAG_CC2 ((uint16_t)0x0004)
942 #define TIM_FLAG_CC3 ((uint16_t)0x0008)
943 #define TIM_FLAG_CC4 ((uint16_t)0x0010)
944 #define TIM_FLAG_COM ((uint16_t)0x0020)
945 #define TIM_FLAG_Trigger ((uint16_t)0x0040)
946 #define TIM_FLAG_Break ((uint16_t)0x0080)
947 #define TIM_FLAG_CC1OF ((uint16_t)0x0200)
948 #define TIM_FLAG_CC2OF ((uint16_t)0x0400)
949 #define TIM_FLAG_CC3OF ((uint16_t)0x0800)
950 #define TIM_FLAG_CC4OF ((uint16_t)0x1000)
951 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
952  ((FLAG) == TIM_FLAG_CC1) || \
953  ((FLAG) == TIM_FLAG_CC2) || \
954  ((FLAG) == TIM_FLAG_CC3) || \
955  ((FLAG) == TIM_FLAG_CC4) || \
956  ((FLAG) == TIM_FLAG_COM) || \
957  ((FLAG) == TIM_FLAG_Trigger) || \
958  ((FLAG) == TIM_FLAG_Break) || \
959  ((FLAG) == TIM_FLAG_CC1OF) || \
960  ((FLAG) == TIM_FLAG_CC2OF) || \
961  ((FLAG) == TIM_FLAG_CC3OF) || \
962  ((FLAG) == TIM_FLAG_CC4OF))
963 
964 /**
965  * @}
966  */
967 
968 /** @defgroup TIM_Input_Capture_Filer_Value
969  * @{
970  */
971 
972 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
973 /**
974  * @}
975  */
976 
977 /** @defgroup TIM_External_Trigger_Filter
978  * @{
979  */
980 
981 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
982 /**
983  * @}
984  */
985 
986 /** @defgroup TIM_Legacy
987  * @{
988  */
989 
990 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
991 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
992 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
993 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
994 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
995 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
996 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
997 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
998 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
999 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
1000 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
1001 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
1002 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
1003 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
1004 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
1005 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
1006 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
1007 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
1008 /**
1009  * @}
1010  */
1011 
1012 /**
1013  * @}
1014  */
1015 
1016 /* Exported macro ------------------------------------------------------------*/
1017 /* Exported functions --------------------------------------------------------*/
1018 
1019 /* TimeBase management ********************************************************/
1020 void TIM_DeInit(TIM_TypeDef* TIMx);
1021 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
1022 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
1023 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
1024 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
1025 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
1026 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
1027 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
1028 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
1029 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
1030 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
1031 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
1032 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
1033 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
1034 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
1035 
1036 /* Output Compare management **************************************************/
1037 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1038 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1039 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1040 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1041 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
1042 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
1043 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
1044 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
1045 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
1046 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
1047 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1048 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1049 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1050 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1051 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1052 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1053 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1054 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1055 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1056 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1057 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1058 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1059 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1060 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1061 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1062 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1063 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1064 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1065 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1066 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1067 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1068 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1069 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1070 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
1071 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
1072 
1073 /* Input Capture management ***************************************************/
1074 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
1075 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
1076 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
1077 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
1078 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
1079 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
1080 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
1081 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1082 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1083 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1084 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1085 
1086 /* Advanced-control timers (TIM1 and TIM8) specific features ******************/
1087 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
1088 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
1089 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
1090 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
1091 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
1092 
1093 /* Interrupts, DMA and flags management ***************************************/
1094 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
1095 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
1096 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
1097 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
1098 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
1099 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
1100 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
1101 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
1102 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
1103 
1104 /* Clocks management **********************************************************/
1105 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
1106 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
1107 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
1108  uint16_t TIM_ICPolarity, uint16_t ICFilter);
1109 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1110  uint16_t ExtTRGFilter);
1111 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
1112  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
1113 
1114 /* Synchronization management *************************************************/
1115 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
1116 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
1117 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
1118 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
1119 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1120  uint16_t ExtTRGFilter);
1121 
1122 /* Specific interface management **********************************************/
1123 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
1124  uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
1125 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
1126 
1127 /* Specific remapping management **********************************************/
1128 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
1129 
1130 #ifdef __cplusplus
1131 }
1132 #endif
1133 
1134 #endif /*__STM32F4xx_TIM_H */
1135 
1136 /**
1137  * @}
1138  */
1139 
1140 /**
1141  * @}
1142  */
1143 
1144 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
TIM_OCInitTypeDef::TIM_OutputState
uint16_t TIM_OutputState
Definition: stm32f4xx_tim.h:83
TIM_ICInitTypeDef::TIM_ICSelection
uint16_t TIM_ICSelection
Definition: stm32f4xx_tim.h:122
TIM_BDTRInitTypeDef::TIM_DeadTime
uint16_t TIM_DeadTime
Definition: stm32f4xx_tim.h:149
TIM_BDTRInitTypeDef::TIM_OSSRState
uint16_t TIM_OSSRState
Definition: stm32f4xx_tim.h:140
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
TIM_OCInitTypeDef::TIM_OCIdleState
uint16_t TIM_OCIdleState
Definition: stm32f4xx_tim.h:100
TIM_BDTRInitTypeDef::TIM_BreakPolarity
uint16_t TIM_BreakPolarity
Definition: stm32f4xx_tim.h:156
TIM_BDTRInitTypeDef::TIM_OSSIState
uint16_t TIM_OSSIState
Definition: stm32f4xx_tim.h:143
TIM_ICInitTypeDef::TIM_ICFilter
uint16_t TIM_ICFilter
Definition: stm32f4xx_tim.h:128
TIM_OCInitTypeDef::TIM_Pulse
uint32_t TIM_Pulse
Definition: stm32f4xx_tim.h:90
TIM_TimeBaseInitTypeDef::TIM_Prescaler
uint16_t TIM_Prescaler
Definition: stm32f4xx_tim.h:51
TIM_OCInitTypeDef::TIM_OutputNState
uint16_t TIM_OutputNState
Definition: stm32f4xx_tim.h:86
TIM_OCInitTypeDef::TIM_OCMode
uint16_t TIM_OCMode
Definition: stm32f4xx_tim.h:80
TIM_ICInitTypeDef::TIM_ICPrescaler
uint16_t TIM_ICPrescaler
Definition: stm32f4xx_tim.h:125
TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter
uint8_t TIM_RepetitionCounter
Definition: stm32f4xx_tim.h:64
TIM_TimeBaseInitTypeDef
TIM Time Base Init structure definition.
Definition: stm32f4xx_tim.h:49
TIM_ICInitTypeDef::TIM_Channel
uint16_t TIM_Channel
Definition: stm32f4xx_tim.h:116
TIM_BDTRInitTypeDef::TIM_Break
uint16_t TIM_Break
Definition: stm32f4xx_tim.h:153
TIM_ICInitTypeDef
TIM Input Capture Init structure definition.
Definition: stm32f4xx_tim.h:113
TIM_TimeBaseInitTypeDef::TIM_Period
uint32_t TIM_Period
Definition: stm32f4xx_tim.h:57
TIM_TypeDef
TIM.
Definition: stm32f4xx.h:862
TIM_TimeBaseInitTypeDef::TIM_ClockDivision
uint16_t TIM_ClockDivision
Definition: stm32f4xx_tim.h:61
TIM_ICInitTypeDef::TIM_ICPolarity
uint16_t TIM_ICPolarity
Definition: stm32f4xx_tim.h:119
TIM_OCInitTypeDef::TIM_OCPolarity
uint16_t TIM_OCPolarity
Definition: stm32f4xx_tim.h:93
TIM_BDTRInitTypeDef::TIM_LOCKLevel
uint16_t TIM_LOCKLevel
Definition: stm32f4xx_tim.h:146
TIM_OCInitTypeDef::TIM_OCNPolarity
uint16_t TIM_OCNPolarity
Definition: stm32f4xx_tim.h:96
TIM_OCInitTypeDef::TIM_OCNIdleState
uint16_t TIM_OCNIdleState
Definition: stm32f4xx_tim.h:104
TIM_OCInitTypeDef
TIM Output Compare Init structure definition.
Definition: stm32f4xx_tim.h:78
TIM_BDTRInitTypeDef
BDTR structure definition.
Definition: stm32f4xx_tim.h:137
TIM_TimeBaseInitTypeDef::TIM_CounterMode
uint16_t TIM_CounterMode
Definition: stm32f4xx_tim.h:54
TIM_BDTRInitTypeDef::TIM_AutomaticOutput
uint16_t TIM_AutomaticOutput
Definition: stm32f4xx_tim.h:159
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