stm32_camera.c

Go to the documentation of this file.

/**
 * \file heivs/stm32_camera.c
 *
 * \brief Camera interface for stm32 processors
 * \author marc dot pignat at hevs dot ch
 */

#include "heivs/stm32_camera.h"
#include "stm32/stm32f4xx_rcc.h"
#include "stm32/stm32f4xx_dma.h"
#include "stm32/stm32f4xx_dcmi.h"
#include "stm32/stm32f4xx_misc.h"
#include "heivs/time.h"

#define MAX_RETRY_COUNT 5

struct dma_xfer_t
{
    void *buffer_base;
    uint32_t buffer_size;
    uint32_t current_base;
    uint32_t current_size;
    uint32_t current_element_size;
    const struct camera_t *cam;
    void *(*next_handler)(const struct camera_t *cam);
    void (*done_handler)(status_e status, const struct camera_t *cam);
    uint32_t continuous;
    uint32_t done;
    uint32_t restart;
    uint32_t dma_error;
    uint32_t one_shot_running;
    status_e one_shot_status;
};

static struct dma_xfer_t xfer;

static void xfer_update(volatile struct dma_xfer_t *xfer)
{
    xfer->current_base += xfer->current_element_size;
    xfer->current_size -= xfer->current_element_size;
}

static status_e xfer_next(volatile struct dma_xfer_t *xfer)
{
    uint32_t target = DMA_GetCurrentMemoryTarget(DMA2_Stream1);

    switch (target)
    {
    case 0:
        target = DMA_Memory_1;
    break;
    case 1:
        target = DMA_Memory_0;
    break;
    default:
        return ERROR_BAD_STATE;
    break;
    }

    DMA_MemoryTargetConfig(DMA2_Stream1, xfer->current_base, target);

    xfer_update(xfer);

    return NO_ERROR;
}

static uint32_t xfer_size(uint32_t size)
{
    while (size > UINT16_MAX)
    {
        size /= 2;
    }

    return size;
}

static status_e xfer_setup(volatile struct dma_xfer_t *xfer)
{
    const struct camera_t *cam = xfer->cam;

    xfer->current_base = (uint32_t)xfer->buffer_base;
    xfer->current_size = camera_get_image_size(cam);
    if (xfer->current_size > xfer->buffer_size)
    {
        return ERROR_TOO_BIG;
    }
    xfer->current_element_size = xfer_size(xfer->current_size);

    return NO_ERROR;
}

static status_e xfer_start(volatile struct dma_xfer_t *xfer)
{
    status_e status;
    DMA_InitTypeDef config;

    DMA_DeInit(DMA2_Stream1);
    DMA_ITConfig(DMA2_Stream1, DMA_IT_HT | DMA_IT_TC | DMA_IT_TE | DMA_IT_FE, ENABLE);
    status = xfer_setup(xfer);
    if (status != NO_ERROR)
    {
        return status;
    }

    config.DMA_Channel = DMA_Channel_1;
    config.DMA_PeripheralBaseAddr = (uint32_t)&DCMI->DR;
    config.DMA_Memory0BaseAddr = xfer->current_base;
    config.DMA_DIR = DMA_DIR_PeripheralToMemory;
    config.DMA_BufferSize = xfer->current_element_size/4;
    config.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
    config.DMA_MemoryInc = DMA_MemoryInc_Enable;
    config.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
    config.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
    config.DMA_Mode = DMA_Mode_Normal;
    config.DMA_Priority = DMA_Priority_VeryHigh;
    config.DMA_FIFOMode = DMA_FIFOMode_Enable;
    config.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
    config.DMA_MemoryBurst = DMA_MemoryBurst_INC4;
    config.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;

    if (xfer->current_size > UINT16_MAX)
    {
        config.DMA_Mode = DMA_Mode_Circular;
    }

    /* DMA2 IRQ channel Configuration */
    DMA_Init(DMA2_Stream1, &config);

    xfer_update(xfer);

    if (xfer->current_size > UINT16_MAX)
    {
        DMA_DoubleBufferModeConfig(DMA2_Stream1, xfer->current_base, DMA_Memory_0);
        DMA_DoubleBufferModeCmd(DMA2_Stream1, ENABLE);
    }

    DMA_Cmd(DMA2_Stream1, ENABLE);

    return NO_ERROR;
}

/**
  * @brief  This function handles DMA2_Stream1 interrupt.
  * @param  None
  * @retval None
  */
static void Camera_DMA_IRQ_Handler(void)
{
    /* FIFO Error interrupt */
    if (DMA_GetFlagStatus(DMA2_Stream1, DMA_FLAG_FEIF1) != RESET)
    {
        /**
         * DMA FIFO error is not necessary a problem because there is a fifo in
         * the DCMI_DR, so let the DCMI_IRQ handle that problem.
         */

        /* Clear the Interrupt flag */
        DMA_ClearFlag(DMA2_Stream1, DMA_FLAG_FEIF1);
    }

    /* Transfer error interrupt */
    if (DMA_GetFlagStatus(DMA2_Stream1, DMA_FLAG_TEIF1) != RESET)
    {
        xfer.restart = 1;
        xfer.dma_error++;

        DMA_ITConfig(DMA2_Stream1, DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_FE, DISABLE);

        if (xfer.dma_error > MAX_RETRY_COUNT || xfer.one_shot_running)
        {
            xfer.done_handler(ERROR_DMA_UNDERRUN, xfer.cam);
            xfer.dma_error = 0;
        }

        xfer.one_shot_running = 0;

        /* Clear the Interrupt flag */
        DMA_ClearFlag(DMA2_Stream1, DMA_FLAG_TEIF1 | DMA_FLAG_DMEIF1);
    }

    /* Half Transfer complete interrupt */
    if (DMA_GetFlagStatus(DMA2_Stream1, DMA_FLAG_HTIF1) != RESET)
    {
        if (!xfer.restart)
        {
            if (xfer.current_size)
            {
                xfer_next(&xfer);
            }
            else
            {
                xfer.done = 1;
                xfer.buffer_base = NULL;
                if (xfer.next_handler != NULL)
                {
                    xfer.buffer_base = xfer.next_handler(xfer.cam);
                }

                if (!(xfer.buffer_base == NULL))
                {
                    xfer_setup(&xfer);
                    xfer_next(&xfer);
                }
            }
        }

        /* Clear the Interrupt flag */
        DMA_ClearFlag(DMA2_Stream1, DMA_FLAG_HTIF1);
    }

    /* Transfer complete interrupt */
    if (DMA_GetFlagStatus(DMA2_Stream1, DMA_FLAG_TCIF1) != RESET)
    {
        if (!xfer.restart)
        {
            if (xfer.done)
            {
                xfer.done = 0;
                xfer.dma_error = 0;
                if (xfer.done_handler)
                {
                    xfer.done_handler(NO_ERROR, xfer.cam);
                }
                xfer.one_shot_running = 0;

                if (!xfer.continuous)
                {
                    DMA_Cmd(DMA2_Stream1, DISABLE);
                }
            }
        }

        /* Clear the Interrupt flag */
        DMA_ClearFlag(DMA2_Stream1, DMA_FLAG_TCIF1);
    }
}

static void Camera_DCMI_IRQ_Handler(void)
{
    uint32_t misr = DCMI->MISR;

    // Clear interrupts
    DCMI->ICR = misr;

    // DCMI overflow (== not enough bandwidth from camera to RAM)
    if (misr & DCMI_MISR_OVF_MIS)
    {
        xfer.restart = 0;
        xfer_start(&xfer);
    }

    // Restart needed because of bad alignment (a breakpoint will cause this)
    if ((uint32_t)xfer.buffer_base+xfer.current_element_size != xfer.current_base)
    {
        if (xfer.continuous)
        {
            xfer_start(&xfer);
        }
    }

    // DMA error : restart
    if (xfer.restart == 1)
    {
        xfer.restart++;
    }
    else if (xfer.restart == 2)
    {
        xfer.restart = 0;
        xfer_start(&xfer);
    }
}

status_e camera_init(const struct camera_t *cam)
{
    status_e status;

    /* Initialize DCMI used pins */
    status = gpio_setup_list(cam->data_pins, cam->data_pins_count);
    if (status != NO_ERROR)
    {
        return status;
    }

    status = gpio_setup_list(cam->control_pins, cam->control_pins_count);
    if (status != NO_ERROR)
    {
        return status;
    }

    if (cam->mco_frequency != 0)
    {
        status = gpio_setup(&cam->mco_pin);
        if (status != NO_ERROR)
        {
            return status;
        }

        /**
         * FIXME : use cam->mco_frequency to choose this frequency
         *
         * For now, use 8 MHz.
         */
        RCC_MCO1Config(RCC_MCO1Source_HSI, RCC_MCO1Div_2); /* MCO1 is 8 MHz */
    }

    /* Enable DMCI clock and reset it */
    RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE);
    RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_DCMI, ENABLE);
    RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_DCMI, DISABLE);

    DCMI->CR &= ~((uint32_t)DCMI_CR_CM     | DCMI_CR_ESS   | DCMI_CR_PCKPOL |
            DCMI_CR_HSPOL  | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 |
            DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1);

    DCMI->CR = DCMI_CR_ENABLE;

    /* Configures the DMA2 to transfer Data from DCMI */
    /* Enable DMA2 clock */
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);

    NVIC_InitTypeDef  NVIC_InitStructure;

    /* DMA2 IRQ channel Configuration */
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
    NVIC_InitStructure.NVIC_IRQChannel = DMA2_Stream1_IRQn ;
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 13;
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
    NVIC_InitStructure.NVIC_Handler = Camera_DMA_IRQ_Handler;
    NVIC_Init(&NVIC_InitStructure);

    /* DCMI IRQ Configuration */
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
    NVIC_InitStructure.NVIC_IRQChannel = DCMI_IRQn ;
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 13;
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
    NVIC_InitStructure.NVIC_Handler = Camera_DCMI_IRQ_Handler;
    NVIC_Init(&NVIC_InitStructure);

    return cam->funcs->init(cam);
}

status_e camera_setup(const struct camera_t *cam, const struct camera_image_options_t *new_options)
{
    status_e status;
    uint32_t continuous_was = xfer.continuous;
    void *(*next_was)(const struct camera_t *cam) = xfer.next_handler;
    void (*done_was)(status_e status, const struct camera_t *cam) = xfer.done_handler;


    if (continuous_was)
    {
        camera_continuous_stop(cam);
    }

    *cam->image_options = *new_options;
    if (cam->funcs->setup)
    {
        status =  cam->funcs->setup(cam);
        if (status != NO_ERROR)
        {
            return status;
        }
    }

    if (continuous_was)
    {
        camera_continuous_start(cam, next_was, done_was, xfer.buffer_size);
    }

    return NO_ERROR;
}

status_e camera_continuous_stop(const struct camera_t *cam)
{
    status_e status;
    timeout_t timeout = time_set_timeout_ms(2000);

    DCMI->IER &= ~DCMI_IER_FRAME_IE;

    /* Wait end of frame */
    while (! (DCMI->RISR & DCMI_RISR_FRAME_RIS))
    {
        if (time_elapsed(timeout))
        {
            break;
        }
    }

    DCMI->ICR = DCMI_ICR_FRAME_ISC;

    DCMI->CR &= ~DCMI_CR_CAPTURE;

    xfer.continuous = 0;
    xfer.next_handler = NULL;
    xfer.done_handler = NULL;

    if (cam->funcs->pause)
    {
        status = cam->funcs->pause(cam);
        if (status != NO_ERROR)
        {
            return status;
        }
    }

    return NO_ERROR;
}

status_e camera_continuous_start(const struct camera_t *cam, void *(*next_handler)(const struct camera_t *), void (*done_handler)(status_e status, const struct camera_t *), size_t size)
{
    status_e status = NO_ERROR;

    if (!next_handler || !done_handler)
    {
        return ERROR_BAD_PARAM;
    }

    if (cam->funcs->start)
    {
        status = cam->funcs->start(cam, 0);
        if (status != NO_ERROR)
        {
            return status;
        }
    }

    memset(&xfer, 0x0, sizeof(xfer));

    xfer.cam = cam;
    xfer.continuous = 1;
    xfer.next_handler = next_handler;
    xfer.done_handler = done_handler;
    xfer.buffer_base = next_handler(cam);
    xfer.buffer_size = size;
    status = xfer_start(&xfer);
    if (status != NO_ERROR)
    {
        return status;
    }

    DCMI->CR &= ~DCMI_CR_CM;
    DCMI->CR |= DCMI_CR_CAPTURE;
    DCMI->IER = DCMI_IER_FRAME_IE | DCMI_IER_OVF_IE;

    return NO_ERROR;
}


static void default_done_handler(status_e status, const struct camera_t *cam)
{
    (void)cam;
    xfer.one_shot_status = status;
}

status_e camera_one_shot_wait(const struct camera_t *cam)
{
    timeout_t timeout = time_set_timeout_ms(1000);

    (void)cam;

    while (xfer.one_shot_running)
    {
        if (time_elapsed(timeout))
        {
            return ERROR_TIMEOUT;
        }
    }

    return xfer.one_shot_status;
}

status_e camera_one_shot_status(const struct camera_t *cam)
{
    (void)cam;

    if (xfer.one_shot_running)
    {
        return ERROR_AGAIN;
    }

    return xfer.one_shot_status;
}


status_e camera_one_shot_start(const struct camera_t *cam, void (*done_handler)(status_e, const struct camera_t *), void *dst, size_t size)
{
    status_e status = NO_ERROR;

    if (cam->funcs->start)
    {
        status = cam->funcs->start(cam, 0);
        if (status != NO_ERROR)
        {
            return status;
        }
    }

    memset(&xfer, 0x0, sizeof(xfer));

    xfer.cam = cam;
    xfer.one_shot_running = 1;
    xfer.next_handler = NULL;
    if (!done_handler)
    {
        done_handler = default_done_handler;
    }
    xfer.done_handler = done_handler;
    xfer.buffer_base = dst;
    xfer.buffer_size = size;
    status = xfer_start(&xfer);
    if (status != NO_ERROR)
    {
        return status;
    }

    DCMI->CR |= DCMI_CR_CM;
    DCMI->CR |= DCMI_CR_CAPTURE;
    DCMI->IER = DCMI_IER_FRAME_IE | DCMI_IER_OVF_IE;

    return NO_ERROR;
}

static uint32_t noverify_camera_get_image_size(const struct camera_t *cam)
{
    switch (cam->image_options->format)
    {
    case IMAGE_FORMAT_RGB565:
            return cam->image_options->xres * cam->image_options->yres * 2;
    break;

    default:
    return 0;
    }
}

uint32_t camera_get_image_size(const struct camera_t *cam)
{
    uint32_t size = noverify_camera_get_image_size(cam);

    return size;
}