stm32_sd.c

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/**
 * \file    heivs/stm32_sd.c
 * \brief   SD memory card access for STM32 boards
 * \author  marc dot pignat at hevs dot ch
 */

#include "heivs/stm32_sd.h"
#include "stm32/stm32f4xx.h"
#include "stm32/stm32f4xx_gpio.h"
#include "stm32/stm32f4xx_rcc.h"
#include "stm32/stm32f4xx_dma.h"
#include "stm32/stm32f4xx_sdio.h"
#include "heivs/stm32_gpio.h"

#include "heivs/time.h"
#include <string.h>

#define SD_TIMEOUT_MS 1000
#define SD_BLOCK_SIZE 512

enum direction_e
{
    DIRECTION_NONE,
    DIRECTION_TX,
    DIRECTION_RX,
};

struct sd_state_t
{
    uint32_t sdhc;
    uint32_t RCA;
    uint32_t sector_count;
    void *buf;
    volatile enum direction_e direction;
};
static struct sd_state_t sd_state;

#define DATATIMEOUT   (0xFFFFFF)  //I simply made this up. A method for computing a realistic values from CSD is described in the specs.

//SDIO Commands  Index
#define CMD0          ((uint8_t)0)
#define CMD8          ((uint8_t)8)
#define CMD55         ((uint8_t)55)
#define ACMD41        ((uint8_t)41)
#define CMD2          ((uint8_t)2)
#define CMD3          ((uint8_t)3)
#define CMD9          ((uint8_t)9)
#define CMD7          ((uint8_t)7)
#define ACMD6         ((uint8_t)6)
#define CMD24         ((uint8_t)24)
#define CMD25         ((uint8_t)25)
#define CMD12         ((uint8_t)12)
#define CMD13         ((uint8_t)13)
#define CMD17         ((uint8_t)17)
#define CMD18         ((uint8_t)18)

//Auxilary defines
#define NORESP        (0x00)
#define SHRESP        (0x40)
#define LNRESP        (0xC0)
#define R3RESP        (0xF40)  //Note this is totaly out of standard. However, becouse of the masking in status = SD_Command it will be processed as SHRESP
//R3 does not contain a valid CRC. Therefore, CCRCFAIL is set and CMDREND is never set for R3.
//To properly process R3, exit the loop CCRCFAIL condition and don't check CMDREND

#define RESP_R1       (0x01)
#define RESP_R1b      (0x02)
#define RESP_R2       (0x03)
#define RESP_R3       (0x04)
#define RESP_R6       (0x05)
#define RESP_R7       (0x06)

static void SD_Panic(uint32_t code, const char *message) {(void)code; (void)message;}

static const struct gpio_t detect_pin = DEF_GPIOC(13, GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_2);
status_e SD_Detect(void)
{
    return gpio_get(&detect_pin) ? ERROR_SD_NOT_PRESENT : NO_ERROR;
}

status_e SD_GetStatus(void)
{
    if (sd_state.direction != DIRECTION_NONE)
    {
        return ERROR_AGAIN;
    }

    return NO_ERROR;
}

static status_e SD_Command(uint32_t cmd, uint32_t resp, uint32_t arg)
{
    uint32_t sd_status;
    timeout_t timeout = time_set_timeout_ms(SD_TIMEOUT_MS);
    //Response must be:
    //0,2:No response (expect cmdsent) ->NORESP
    //1:Short Response  (expect cmdrend and ccrcfail) ->SHRESP
    //3:Long Response   (expect cmdrend and ccrcfail) ->LNRESP

    //Clear the Command Flags
    SDIO->ICR = (0x3<<22)|0x3ff;

    SDIO->ARG = arg; //First adjust the argument (because I will immediately enable CPSM next)
    SDIO->CMD = (uint32_t) (cmd & SDIO_CMD_CMDINDEX)
            | (resp & SDIO_CMD_WAITRESP) | (0x0400); //The last argument is to enable CSPM

    //Block till we get a response
    if (resp == NORESP)
    {
        //We should wait for CMDSENT
        while (1)
        {
            sd_status = SDIO->STA;

            if (sd_status & SDIO_STA_CMDSENT)
            {
                break;
            }

            if (sd_status & SDIO_STA_CTIMEOUT)
            {
                return ERROR_TIMEOUT;
            }

            if (time_elapsed(timeout))
            {
                return ERROR_TIMEOUT;
            }
        }
    }
    else
    {  //SHRESP or LNRESP or R3RESP
        //We should wait for CMDREND or CCRCFAIL

        while (1)
        {
            sd_status = SDIO->STA;

            if (sd_status & SDIO_STA_CTIMEOUT)
            {
                SD_Panic(cmd, "SDIO: Command Timeout Error\n");
                return ERROR_TIMEOUT;
            }

            if (!(sd_status & SDIO_STA_CMDACT))
            {
                if (sd_status & (SDIO_STA_CMDREND | SDIO_FLAG_CCRCFAIL))
                {
                    break;
                }
            }

            if (time_elapsed(timeout))
            {
                return ERROR_TIMEOUT;
            }
        }
    }

    //Check to see if the response is valid
    //We consider all R3 responses without a timeout as a valid response
    //It seems CMDSENT and CMDREND are mutually exlusive. (though I am not sure. Check this later)
    if (sd_status & SDIO_FLAG_CCRCFAIL)
    {
        if (resp == R3RESP)
        {
            return NO_ERROR;
        }

        if (resp == LNRESP)
        {
            return NO_ERROR;
        }
        SD_Panic(cmd, "SDIO: Command CRC Error\n");
        return ERROR_SD_ACCESS_FAILED;
    }

    return NO_ERROR;

}

static status_e SD_Response(uint32_t *response, uint32_t type)
{
    //I mainly use this to block the execution in case an unexpected response is received.
    //Actually I don't need this at all. However, just for the sake of extra information I keep this. All I reall need is for this function to return SDIO->RESP1
    //In the main code, I don't use the retun values at all. Perhaps I ought to have used void.

    //R1 Responses
    if ((type == RESP_R1) || (type == RESP_R1b))
    {
        *response = SDIO->RESP1;
        if (*response & (uint32_t) 0xFDFFE008)
        { //All error bits must be zero
            SD_Panic(SDIO->RESPCMD, "SDIO:Response Error\n");
            return ERROR_SD_ACCESS_FAILED;
        }
        return NO_ERROR;   //(*response & 0x1F00)>>8; //Return the card status
    }

    if (type == RESP_R2)
    { //CSD or CSI register. 128 bit
        *response++ = SDIO->RESP1;
        *response++ = SDIO->RESP2;
        *response++ = SDIO->RESP3;
        *response = SDIO->RESP4;

        return NO_ERROR; //0;
    }

    if (type == RESP_R3)
    { //OCR
        if (SDIO->RESPCMD != 0x3F)
        {
            SD_Panic(SDIO->RESPCMD, "SDIO:Unexpected command index\n");
            return ERROR_SD_ACCESS_FAILED;
        } //CMD index for R3 must be 0x3F
        *response = SDIO->RESP1;  //Equals to OCR
        return NO_ERROR;  //0;
    }

    if (type == RESP_R6)
    { //RCA Response
        if (SDIO->RESPCMD != 0x03)
        {
            SD_Panic(SDIO->RESPCMD, "SDIO:Unexpected command index\n");
            return ERROR_SD_ACCESS_FAILED;
        } //Only cmd3 generates R6 response
        *response = SDIO->RESP1;  //Equals to OCR

        return NO_ERROR; //(*response)>>16; //Return is equal to RCA. (The first 16 bit is equal to status)
    }
    else
    {  //RESP_R7:Card Interface condition. Obtained after CMD8
        if (SDIO->RESPCMD != 0x08)
        {
            SD_Panic(SDIO->RESPCMD, "SDIO:Unexpected command index\n");
            return ERROR_SD_ACCESS_FAILED;
        } //Only cmd8 generates R7 response
        *response = SDIO->RESP1;
        if ((*response & 0xFF) != 0xAA)
        {
            SD_Panic(CMD8, "SDIO:Pattern did not match\n");
            return ERROR_SD_ACCESS_FAILED;
        } //Only cmd8 generates R7 response
        return NO_ERROR; //((*response) & 0xFF00)>>8; //Echo back value
    }
}

static uint32_t dmable_buffer[SD_BLOCK_SIZE/sizeof(uint32_t)];

static void SD_StartBlockTransfer(uint8_t *buf, uint32_t cnt,   enum direction_e direction)
{
    DMA_InitTypeDef SDDMA_InitStructure;

    DMA_ClearFlag(DMA2_Stream3,
            DMA_FLAG_FEIF3 | DMA_FLAG_DMEIF3 | DMA_FLAG_TEIF3 | DMA_FLAG_HTIF3
                    | DMA_FLAG_TCIF3);

    /* DMA2 Stream3  or Stream6 disable */
    DMA_Cmd(DMA2_Stream3, DISABLE);

    /* DMA2 Stream3  or Stream6 Config */
    DMA_DeInit(DMA2_Stream3);

    SDDMA_InitStructure.DMA_Channel = DMA_Channel_4;
    SDDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &SDIO->FIFO;
    SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) dmable_buffer;

    if (direction == DIRECTION_TX)
    {
        memcpy(dmable_buffer, buf, SD_BLOCK_SIZE);
        SDDMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
    }
    else
    {
        SDDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
    }
    SDDMA_InitStructure.DMA_BufferSize = 0;
    SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
    SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
    SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
    SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
    SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
    SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
    SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
    SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
    SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4;
    SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4;
    DMA_Init(DMA2_Stream3, &SDDMA_InitStructure);
    DMA_ITConfig(DMA2_Stream3, DMA_IT_TC, ENABLE);
    DMA_FlowControllerConfig(DMA2_Stream3, DMA_FlowCtrl_Peripheral);

    /* DMA2 Stream3  or Stream6 enable */
    DMA_Cmd(DMA2_Stream3, ENABLE);

    ////PART II::::Adjust and enable SDIO Peripheral
    //Clear the Data status flags
    SDIO->ICR = (SDIO_STA_DCRCFAIL | SDIO_STA_DTIMEOUT | SDIO_STA_TXUNDERR
            | SDIO_STA_RXOVERR | SDIO_STA_DATAEND | SDIO_STA_STBITERR
            | SDIO_STA_DBCKEND);

    //First adjust the Dtimer and Data length
    SDIO->DTIMER = (uint32_t) DATATIMEOUT;
    SDIO->DLEN = cnt;

    //Now adjust DCTRL (and enable it at the same time)
    uint32_t tempreg;
    tempreg = 0;  //Reset value
    tempreg |= (uint32_t) 9 << 4; //Block size is SD_BLOCK_SIZE Compute log2(BlockSize) and shift 4bit
    tempreg |= 1 << 3; //Enable the DMA
    tempreg |= 0 << 2; //DTMode=Block Transfer (Actualy this is the reset value. Just a remainder)
    if (direction == DIRECTION_RX)
    {
        tempreg |= SDIO_DCTRL_DTDIR;
    }
    tempreg |= 1; //DPSM is enabled
    //Keep the rest at 0 => OTher SDIO functions is disabled(we don't need them)
    SDIO->DCTRL = tempreg;
    //End of PART II

    //Warn everyone that there may be a transfer in progress
    sd_state.direction = direction;
    sd_state.buf = buf;
}

status_e SD_LowLevel_Init(void)
{
    uint32_t tempreg;

    gpio_setup(&detect_pin);
    GPIO_InitTypeDef GPIO_InitStructure;

    // GPIOC and GPIOD Periph clock enable
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD, ENABLE);

    //Initialize the pins
    GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_SDIO);
    GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_SDIO);
    GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_SDIO);

    // Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
    GPIO_Init(GPIOC, &GPIO_InitStructure);

    // Configure PD.02 CMD line
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
    GPIO_Init(GPIOD, &GPIO_InitStructure);

    // Configure PC.12 pin: CLK pin
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
    GPIO_Init(GPIOC, &GPIO_InitStructure);

    //Enable the SDIO APB2 Clock
    RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE);

    // Enable the DMA2 Clock
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);

    //Initialize the SDIO (with initial <400Khz Clock)
    tempreg = 0;  //Reset value
    tempreg |= SDIO_CLKCR_CLKEN;  //Clock is enabled
    tempreg |= (uint32_t) 0x76;  //Clock Divider. Clock=48000/(118+2)=400Khz
    //Keep the rest at 0 => HW_Flow Disabled, Rising Clock Edge, Disable CLK ByPass, Bus Width=0, Power save Disable
    SDIO->CLKCR = tempreg;

    //Power up the SDIO
    SDIO->POWER = 0x03;

    return NO_ERROR;
}

static status_e compute_size(struct sd_state_t *state, uint32_t *CSD_Tab)
{
    uint8_t tmp;
    uint32_t tmp32;
    uint32_t read_bl_len;

    /*!< Byte 5 */
    tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16);

    read_bl_len = tmp & 0x0F;

    if (!state->sdhc)
    {
        uint32_t mul;
        tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8);

        tmp32 = (tmp & 0x03) << 10;

        /*!< Byte 7 */
        tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF);
        tmp32 |= (tmp) << 2;

        /*!< Byte 8 */
        tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24);
        tmp32 |= (tmp & 0xC0) >> 6;

        /*!< Byte 9 */
        tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16);
        mul = (tmp & 0x03) << 1;
        /*!< Byte 10 */
        tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8);
        mul |= (tmp & 0x80) >> 7;

        state->sector_count = (tmp32 + 1) ;
        state->sector_count *= (1 << (mul + 2));
        state->sector_count *= (1<<read_bl_len)/512;
    }
    else
    {
        uint32_t tmp32;

        /*!< Byte 7 */
        tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF);
        tmp32 = (tmp & 0x3F) << 16;

        /*!< Byte 8 */
        tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24);

        tmp32 |= (tmp << 8);

        /*!< Byte 9 */
        tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16);

        tmp32 |= (tmp);

        /*!< Byte 10 */
        tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8);

        state->sector_count = tmp32 *1024;
    }

    return NO_ERROR;
}

status_e SD_Init(void)
{
    timeout_t timeout = time_set_timeout_ms(SD_TIMEOUT_MS);
    status_e status;
    //uint32_t data;
    uint32_t response;
    uint32_t tempreg;

    //CMD0: GO_IDLE_STATE (No Response)
    status = SD_Command(CMD0, NORESP, 0);
    if (status != NO_ERROR)
    {
        return status;
    }

    //CMD8: SEND_IF_COND  //Response to CMD8 is R7. But I will ignore that response
    status = SD_Command(CMD8, SHRESP, 0x000001AA); //Non v2.0 compliant sd's will cause panic here due to the timeout
    if (status != NO_ERROR)
    {
        return status;
    }
    status = SD_Response(&response, RESP_R7); //AA is the check pattern. If response does not match with it, execution will be blocked in panic
    if (status != NO_ERROR)
    {
        return status;
    }

    while (1)
    {
        ////Send ACMD41
        //CMD55
        status = SD_Command(CMD55, SHRESP, 0); //Note that argument should be RCA. But at this point RCA of SD is 0. (It will be changed after cmd3)
        status = SD_Response(&response, RESP_R1);

        //ACMD41 (Response is R3 which does not contain any CRC)
        //Second argument in the argument indicates that host supports SDHC. We will check acmd41 response if the SD is SC or HC
        status = SD_Command(ACMD41, R3RESP, (uint32_t) 0x80100000 | (uint32_t) 0x40000000);
        status = SD_Response(&response, RESP_R3);

        //Check the ready status in the response (R3)
        if ((response >> 31) == 1)
        {  //When card is busy this bit will be 0
            //Card is now initialized. Check to see if SD is SC or HC
            sd_state.sdhc = (response & 0x40000000) >> 30;  //1=HC, 0=SC
            break;
        }

        if (time_elapsed(timeout))
        {
            SD_Panic(ACMD41, "SDIO:ACMD41 Timeout\n");
            return ERROR_TIMEOUT;
        }
    }

    //Now we are in the Ready State. Ask for CID using CMD2
    //Response is R2. RESP1234 are filled with CID. I will ignore them
    status = SD_Command(CMD2, LNRESP, 0);
    if (status != NO_ERROR)
    {
        return status;
    }

    uint32_t cid[4];
    status = SD_Response(cid, RESP_R2);
    if (status != NO_ERROR)
    {
        return status;
    }

    //Now the card is in the identification mode. Request for the RCA number with cmd3
    status = SD_Command(CMD3, SHRESP, 0);
    if (status != NO_ERROR)
    {
        return status;
    }

    status = SD_Response(&response, RESP_R6);
    if (status != NO_ERROR)
    {
        return status;
    }
    //Read the RCA
    sd_state.RCA = response >> 16;

    //Now the card is in stand-by mode. From this point on I can change frequency as I wish (max24MHz)

    //Use cmd9 to read the card specific information
    //Response is R2 with CSI. I will ignore the response
    status = SD_Command(CMD9, LNRESP, (sd_state.RCA << 16));
    if (status != NO_ERROR)
    {
        return status;
    }

    uint32_t csd[4];
    status = SD_Response(csd, RESP_R2);
    if (status != NO_ERROR)
    {
        return status;
    }

    status = compute_size(&sd_state, csd);
    if (status != NO_ERROR)
    {
        return status;
    }

    //Put the Card in the tranfer mode using cmd7. (I will change the clock spped later together with bus width)
    //Bus width can only be changed in transfer mode
    status = SD_Command(CMD7, SHRESP, (sd_state.RCA << 16));
    if (status != NO_ERROR)
    {
        return status;
    }
    status = SD_Response(&response, RESP_R1);
    if (status != NO_ERROR)
    {
        return status;
    }

    //Change the bus-width with cmd6
    //CMD55
    status = SD_Command(CMD55, SHRESP, (sd_state.RCA << 16)); //Note the real RCA in the argument
    if (status != NO_ERROR)
    {
        return status;
    }

    status = SD_Response(&response, RESP_R1);
    if (status != NO_ERROR)
    {
        return status;
    }

    //ACMD6
    //status = SD_Command(ACMD6, SHRESP, 0x02);
    status = SD_Command(ACMD6, SHRESP, 0x00);
    if (status != NO_ERROR)
    {
        return status;
    }

    status = SD_Response(&response, RESP_R1);
    if (status != NO_ERROR)
    {
        return status;
    }

    //Configure SDIO->CLKCr for wide-bus width and new clock
    tempreg = 0;  //Reset value
    /*
     tempreg|=(0x01)<<11; //4 bit Bus Width
     */
    tempreg |= (0x00) << 11; // 1 bit bus
    tempreg |= SDIO_CLKCR_CLKEN;  //Clock is enabled
    //Keep the rest at 0=> HW_Flow:Disabled, Rising Edge, Disable bypass, Power save Disable, Clock Division=0
    //As the clock divider=0 => New clock=48/(Div+2)=48/2=24
    SDIO->CLKCR = tempreg;

    //Now we can start issuing read/write commands
    return NO_ERROR;
}

status_e SD_GetSectorCount(uint32_t *count)
{
    *count = sd_state.sector_count;
    return NO_ERROR;
}

status_e SD_WaitTransmissionEnd(void)
{
    timeout_t timeout = time_set_timeout_ms(SD_TIMEOUT_MS);
    //This function first checks if there is an ogoing tranmission and block till it ends.
    //It then checks the data flags to see if there is an error. In case of an error it blocks
    //Before the start of data transmission the data flags are all cleared. Therefore, calling this fucntion after a real transmission works as expected.

    ////Check if there is an ongoing transmission
    //Check if the DMA is disabled (SDIO disables the DMA after it is done with it)
    while (1)
    {
        if (!(DMA2_Stream3->CR & DMA_SxCR_EN))
        {
            break;
        }

        if (time_elapsed(timeout))
        {
            return ERROR_TIMEOUT;
        }
    }

    //Wait for the DMA Interrupt flags if there exist a previous SDIO transfer.
    if (sd_state.direction != DIRECTION_NONE)
    {
        if (DMA2->LISR
                & (DMA_LISR_TCIF3 | DMA_LISR_TEIF3 | DMA_LISR_DMEIF3
                        | DMA_LISR_FEIF3))
        {
            if (!(DMA2->LISR & DMA_LISR_TCIF3))
            { //A DMA error has occured. Panic!
                SD_Panic(DMA2->LISR, "SDIO:DMA Error");
                return ERROR_SD_ACCESS_FAILED;
            }
        }
    }

    while (1)
    {
        if (!(SDIO->STA & (SDIO_STA_RXACT | SDIO_STA_TXACT)))
        {
            break;
        }

        if (time_elapsed(timeout))
        {
            return ERROR_TIMEOUT;
        }
    }

    //if there exist a previous transmission, check if the transmission has been completed without error
    if (sd_state.direction != DIRECTION_NONE)
    {
        //I will block here till I get a data response
        while (!(SDIO->STA
                & (SDIO_STA_DCRCFAIL | SDIO_STA_DTIMEOUT | SDIO_STA_DBCKEND
                        | SDIO_IT_STBITERR)))
        {
        };
        if (!(SDIO->STA & SDIO_STA_DBCKEND))
        {  //An Error has occured.
            SD_Panic(SDIO->STA, "SDIO:Data Transmission Error\n");
            return ERROR_SD_ACCESS_FAILED;
        }
    }

    //If we are here, we can be sure that there is no ongoing transmission any more
    if (sd_state.direction == DIRECTION_RX)
    {
        memcpy(sd_state.buf, dmable_buffer, SD_BLOCK_SIZE);
    }
    sd_state.direction = DIRECTION_NONE;

    return NO_ERROR;
}

status_e SD_WriteSingleBlock(const void *_buf, uint32_t blk)
{
    status_e status;
    const uint8_t *buf = _buf;
    uint32_t WriteAddr;
    uint32_t response;

    //uint32_t response;
    WriteAddr = blk * SD_BLOCK_SIZE;
    if (sd_state.sdhc == 1)
    {  //High Capacity
        WriteAddr = blk;
    }

    //CMD24:WRITE_SINGLE_BLOCK
    status = SD_Command(CMD24, SHRESP, WriteAddr);
    if (status != NO_ERROR)
    {
        return status;
    }

    status = SD_Response(&response, RESP_R1);
    if (status != NO_ERROR)
    {
        return status;
    }

    //Card is now waiting some data from the Data lines. Start actual data transmission
    SD_StartBlockTransfer((void *)buf, SD_BLOCK_SIZE, DIRECTION_TX);

    //Wait for transmission to end
    status = SD_WaitTransmissionEnd();
    if (status != NO_ERROR)
    {
        return status;
    }

    return NO_ERROR;
}

status_e SD_ReadSingleBlock(void *_buf, uint32_t blk)
{
    status_e status;

    uint8_t *buf = _buf;
    uint32_t ReadAddr;
    uint32_t response;

    //uint32_t response;
    ReadAddr = blk * SD_BLOCK_SIZE;
    if (sd_state.sdhc == 1)
    {  //High Capacity
        ReadAddr = blk;
    }

    //Send CMD17:READ_SINGLE_BLOCK
    status = SD_Command(CMD17, SHRESP, ReadAddr);
    if (status != NO_ERROR)
    {
        return status;
    }
    status = SD_Response(&response, RESP_R1);
    if (status != NO_ERROR)
    {
        return status;
    }

    //Card is now ready to send some data from the Data lines. Start actual data transmission
    SD_StartBlockTransfer(buf, SD_BLOCK_SIZE, DIRECTION_RX);

    //Wait for transmission to end
    status = SD_WaitTransmissionEnd();
    if (status != NO_ERROR)
    {
        return status;
    }

    return NO_ERROR;
}

#ifdef SD_MULTIBLOCK_WRITE
#warning SD_MULTIBLOCK_WRITE is completely untested
//Private Write buffers
static uint8_t DatBuf[SD_BLOCK_SIZE * 2]; //2 blocks (One will be in transit while other is being filled)
static uint8_t *pDatBuf = DatBuf;
static uint32_t BufCnt = 0;
#endif

#ifdef SD_MULTIBLOCK_WRITE
status_e SD_StartMultipleBlockWrite(uint32_t blk)
{
    status_e status;

    uint32_t WriteAddr;
    uint32_t response;

    //uint32_t response;
    WriteAddr = blk * SD_BLOCK_SIZE;
    if (sd_state.sdhc == 1)
    {  //High Capacity
        WriteAddr = blk;
    }

    //CMD25:WRITE_MULT_BLOCK with argument data address
    status = SD_Command(CMD25, SHRESP, WriteAddr);
    if (status != NO_ERROR)
    {
        return status;
    }
    status = SD_Response(&response, RESP_R1);
    if (status != NO_ERROR)
    {
        return status;
    }

    //Clear any flags
    SDIO->ICR = (uint32_t) 0xA003FF;

    return NO_ERROR;
}

status_e SD_StopMultipleBlockWrite(void)
{
    status_e status;
    uint32_t response;

    //If there is previously programmed communication, wait for it to end first
    status = SD_WaitTransmissionEnd();
    if (status != NO_ERROR)
    {
        return status;
    }

    //CMD12:STOP_TRANSMISSION
    status = SD_Command(CMD12, SHRESP, 0);
    status = SD_Response(&response, RESP_R1b);
    //Discard the untransferred buffer
    pDatBuf = DatBuf;
    BufCnt = 0;

    while (((response & 0x100) >> 8) == 0)
    {
        //After CMD12, SD Card puts itself to the prg mode, by pulling D0 to low.
        //DPSM is not aware of this. (I hope it is aware of this during multiblock communication. I need to verify this.
        //If it is not, then I have to repeat the same procedure after each block during multiblock write which will cause too much overhead)
        //Check Card status with CMD13 till, we get READY_FOR_DATA response
        //CMD13:Send Status
        status = SD_Command(CMD13, SHRESP, sd_state.RCA << 16);
        status = SD_Response(&response, RESP_R1b);
    }
    return NO_ERROR;
}

status_e SD_WriteData(uint8_t *buf, uint32_t cnt)
{
    status_e status;

    while (cnt > 0)
    {
        //Copy the data to internal buffer
        *pDatBuf = *buf;
        pDatBuf++;
        buf++;
        cnt--;
        BufCnt++;

        if (BufCnt == SD_BLOCK_SIZE)
        {    //Half Buffer is full.
            //Write Buffer to the SD
            status = SD_WaitTransmissionEnd(); //Wait for any previous transmission
            if (status != NO_ERROR)
            {
                return status;
            }
            //Wait for busy.
            //With SPI we can check this by reading the dataline. SD stops holding the data line when it is not busy.
            //However in SDIO, the only way seems to use CMD13.
            //I am going to skip this part assuming that DPSM handles this properly.
            SD_StartBlockTransfer(pDatBuf - SD_BLOCK_SIZE, SD_BLOCK_SIZE, DIRECTION_TX);

            //Switch to other half (if necessary)
            if (pDatBuf == (DatBuf + (SD_BLOCK_SIZE * 2)))
            {
                pDatBuf = DatBuf;
            }

            //Reset Buffer counter
            BufCnt = 0;
        }
    }
    return NO_ERROR;
}
#endif /* SD_MULTIBLOCK_WRITE */